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2020 – today
- 2025
[j3]Ho-Sung Lee
, Ik-Hyeon Jeon, Jiwon Lee, Hyeonjun Cheon, Joo-Hyung Chae:
URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros. IEEE Access 13: 34060-34069 (2025)- [j2]Sangjun Hwang, Jo-Hak Jeong, Hee-Tae Kim, Jungwoo Bong, Ho-Sung Lee, Bhishma Pandit, Gyeore Lee, Donggu Im, Sung Haeng Cho, Hyeon-Sik Jang, Byung Jin Cho, Keun Heo:
Empirical Modeling and Performance Evaluation of Monolithic-3D Dynamic Random-Access Memory. IEEE Access 13: 39466-39472 (2025) - [j1]Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Eun-Bi Koh, Joo-Hyung Chae:
A Dual-Multiplication-Mode and Reconfigurable Digital Compute-in-Memory Macro Using Precharge-Controlled 4T1C eDRAM. IEEE Trans. Very Large Scale Integr. Syst. 33(10): 2680-2689 (2025) - 2024
- [c3]Ho-Sung Lee, Joo-Hyung Chae:
A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations. ICEIC 2024: 1-4 - [c2]Jiwon Lee, Hyeonjun Cheon, Ho-Sung Lee, Ik-Hyeon Jeon, Joo-Hyung Chae:
Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed. ISOCC 2024: 167-169 - [c1]Hyeonjun Cheon, Ho-Sung Lee, Jiwon Lee, Ik-Hyeon Jeon, Joo-Hyung Chae:
A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes. ISOCC 2024: 169-170
Coauthor Index
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