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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 33
Volume 33, Number 1, January 2025
- Hyoseok Song
, Kwangmin Kim, Gain Kim, Byungsub Kim:
A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization. 1-9 - Jie Ding, Fuming Liu, Kuan Deng, Zihan Zheng, Jingnan Zheng, Yongzhen Chen, Jiangfeng Wu:
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration. 10-20 - Haitao Du, Hairui Zhu, Song Chen, Yi Kang:
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling. 21-34 - Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai:
A 0.05-1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications. 35-46 - Yu Liu, Yupeng Shen, Mingliang Chen, Hui Xu, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu:
A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC. 47-51 - Tianzhu Xiong, Yuyang Ye, Xin Si, Jun Yang:
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. 52-65 - Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego:
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators. 66-74 - Seung-Hwan Bae, Hyuk-Jae Lee, Hyun Kim:
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution. 75-87 - Jie Li, Chuanlun Zhang, Wenxuan Yang, Heng Li, Xiaoyan Wang, Chuanjun Zhao, Shuangli Du, Yiguang Liu:
FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation. 88-101 - Zhichao Chen, Ali H. Hassan, Rhesa Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta:
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. 102-113 - Anawin Opasatian, Makoto Ikeda:
Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier. 114-127 - Ken Li, Tian Xie, Tzu-Han Wang, Shaolan Li:
VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator. 128-139 - Tianning Gao, Yifan Wang, Ming Zhu, Xiulong Wu, Dian Zhou, Zhaori Bi:
An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. 140-153 - Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu:
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. 154-167 - Jhe-En Lin, Shen-Iuan Liu:
A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE. 168-178 - Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam:
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory. 179-192 - Dongkwun Kim, Zhaoqing Wang, Paul Xuanyuanliang Huang, Pavan Kumar Chundi, Suhwan Kim, Andres A. Blanco, Ram K. Krishnamurthy, Mingoo Seok:
A 4.2-to-0.5-V, 0.8-μA-0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor. 193-206 - Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. 207-220 - Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang:
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V. 221-233 - Zhaolin Yang, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. 234-247 - Shuming Guo, Yinyin Lin, Hao Wang, Yao Li, Chongyan Gu, Weiqiang Liu, Yijun Cui:
A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications. 248-260 - Xingye Liu, Paul Ampadu:
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation. 261-274 - Alexandre Almeida da Silva, Lucas Nogueira, Alexandre Coelho, Jarbas A. N. Silveira, César A. M. Marcon:
Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically-Partially Connected 3D-NoC. 275-287 - Lakshmi Bhanuprakash Reddy Konduru, Vikramkumar Pudi, Balasubramanyam Appina:
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. 288-292 - Zhihao Zhou, Wei Zhang, Xinyi Guo, Jianhan Zhao, Yanyan Liu:
High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes. 293-297 - Yiwei Chang, Zhichuan Guo:
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks. 298-302
Volume 33, Number 2, February 2025
- Zhan Qu, Zhenjiao Chen, Xingqiang Shi, Ya Zhao, Guohe Zhang, Feng Liang:
Multiobjective Optimization of Class-F Oscillators. 303-314 - Shiro Dosho, Ludovico Minati, Kazuki Maari, Shungo Ohkubo, Hiroyuki Ito:
A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier. 315-325 - Chiara Venezia, Andrea Ballo, Alfio Dario Grasso, Alessandro Rizzo, Calogero Ribellino, Salvatore Pennisi:
46-nA High-PSR CMOS Buffered Voltage Reference With 1.2-5 V and -40 ◦C to 125 ◦C Operating Range. 326-336 - Ebenezer C. Usih, Naimul Hassan, Alexander J. Edwards, Felipe García-Sánchez, Pedram Khalili Amiri, Joseph S. Friedman:
Toggle SOT-MRAM Architecture With Self-Terminating Write Operation. 337-345 - Sudipta Das, Samuel Riedel, Mohamed Naeim, Moritz Brunion, Marco Bertuletti, Luca Benini, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic:
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. 346-357 - Gauthaman Murali, Min Gyu Park, Sung Kyu Lim:
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators. 358-370 - Lixun Wang, Yuejun Zhang, Pengjun Wang, Jianguo Yang, Huihong Zhang, Gang Li, Qikang Li:
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices. 371-383 - Tiancheng Cao, Weihao Yu, Yuan Gao, Chen Liu, Tantan Zhang, Shuicheng Yan, Wang Ling Goh:
Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications. 384-394 - Shushi Chen, Leilei Huang, Zhao Zan, Xiaoyang Zeng, Yibo Fan:
An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC. 395-407 - Yazheng Tu, Shi Bai, Jinjun Xiong, Jiafeng Xie:
SCOPE: Schoolbook-Originated Novel Polynomial Multiplication Accelerators for NTRU-Based PQC. 408-420 - Ruichang Jiang, Wenbin Ye:
Hardware-Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA. 421-434 - Chao Ji, Xiaohu You, Chuan Zhang, Christoph Studer:
Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation. 435-448 - Ruijun Ma, Stefan Holst, Hui Xu, Xiaoqing Wen, Senling Wang, Jiuqi Li, Aibin Yan:
Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. 449-461 - Seung Ho Shin, Hayoung Lee, Sungho Kang:
Effective Parallel Redundancy Analysis Using GPU for Memory Repair. 462-474 - Shuo Cai, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu:
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications. 475-487 - Youngki Moon, Seung Ho Shin, Seokjun Jang, Duyeon Won, Sungho Kang:
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM. 488-498 - Huarun Chen, Yijun Liu, Wujian Ye, Jialiang Ye, Yuehai Chen, Shaozhen Chen, Chao Han:
Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform. 499-511 - Zhiquan Wan, Zhipeng Cao, Shunbin Li, Peijie Li, Qingwen Deng, Weihao Wang, Kun Zhang, Guandong Liu, Ruyun Zhang, Qinrang Liu:
Architectural Exploration for Waferscale Switching System. 512-524 - Yuanbo Wang, Liang Chang, Jingke Wang, Pan Zhao, Jiahao Zeng, Xin Zhao, Wuyang Hao, Liang Zhou, Haining Tan, Yinhe Han, Jun Zhou:
PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique. 525-536 - Akhil Reddy Pakala, Zhiyu Chen, Kaiyuan Yang:
MBSNTT: A Highly Parallel Digital In-Memory Bit-Serial Number Theoretic Transform Accelerator. 537-545 - Jia-Li Duan, Chi Zhang, Li-Hui Wang, Lei Shen:
SMBHA: A System-Level Multicore BGV Hardware Accelerator Based on FPGA. 546-557 - Pedro Tauã Lopes Pereira, Patrícia Ücker Leleu da Costa, Eduardo A. C. da Costa, Paulo F. Flores, Sergio Bampi:
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers. 558-562 - Dingyang Zou, Gaoche Zhang, Xu Zhang, Meiqi Wang, Zhongfeng Wang:
An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators. 563-567 - Wanbin Zha, Jiangtao Xu, Kaiming Nie, Zhiyuan Gao:
A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors. 568-572 - Yuxin Ji, Yuhang Zhang, Changyan Chen, Jian Zhao, Fakhrul Zaman Rokhani, Yehea Ismail, Yongfu Li:
A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI. 573-577 - Chenjia Xie, Zhuang Shao, Ning Zhao, Xingyuan Hu, Yuan Du, Li Du:
A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations. 578-582 - Quanzhen Liang, Xiao Wang, Kuisong Wang, Yuepeng Yan, Xiaoxin Liang:
Analysis and Design of Wideband GaAs Digital Step Attenuators. 583-587 - Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang:
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. 588-592 - Jiliang Liu, Huidong Zhao, Zhi Li, Kangning Wang, Shushan Qiao:
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit. 593-597 - Jahyun Koo, Hyunwoo Son, Jae-Yoon Sim:
A 9.6-nW Wake-Up Timer With RC-Referenced Subharmonic Locking Using Dual Leakage-Based Oscillators. 598-602
Volume 33, Number 3, March 2025
- Mircea R. Stan:
Editorial: Renewed Excellence for 2025-2026. 603-626 - Changle Zhi, Gang Dong, Deguang Yang, Daihang Liu, Yinghao Feng, Yang Wang, Zhangming Zhu:
Electrical and Thermal Characteristics Optimization in Interposer-Based 2.5-D Integrated Circuits. 627-637 - Felix Burkhardt, Florian Protze, Frank Ellinger:
A Single-Ended High-Voltage-Compliant 11-bit Current-Steering Digital-to-Analog Converter for Adaptive Noise Cancellation in Power Over Data Line Networks. 638-650 - Yuhong Lu, Ting-An Yen, Rakshit Dambe Nayak, Shashank Alevoor, Bhushan Talele, Spoorti Patil, Keith Kunz, Bertan Bakkaloglu:
A Novel Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR nMOS LDOs. 651-661 - Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Taehwan Kim, Chulwoo Kim:
A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. 662-672 - Yechen Tian, Yutong Zhang, Junjie Gu, Hao Xu, Weitian Liu, Rui Yin, Zongming Duan, Hao Gao, Na Yan:
Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver. 673-684 - Weihao Wang, Kong-Pang Pun:
An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop. 685-696 - Srishti Agrawal, Rakesh Kumar Palani, Sweta Tripathi:
Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars. 697-706 - Zhaoteng Meng, Lin Shu, Jianing Zeng, Zhan Li, Kailin Lv, Haoyue Yang, Jie Hao:
MASL-AFU: A High Memory Access Efficiency 2-D Scalable LUT-Based Activation Function Unit for On-Device DNN Training. 707-719 - Yong-Tai Chen, Yen-Ting Chiu, Hao-Jiun Tu, Chao-Tsung Huang:
Falcon: A Fused-Layer Accelerator With Layer-Wise Hybrid Inference Flow for Computational Imaging CNNs. 720-732 - Eduardo Antonio Cesar da Costa, Morgana Macedo Azevedo da Rosa:
RCU- 2m: A VLSI Radix- 2m Cubic Unit. 733-745 - Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Hideharu Amano, Tohru Mogami, Yoshio Mita, Makoto Ikeda, Tadahiro Kuroda:
Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication. 746-756 - Jingqi Zhang, Zhiming Chen, Mingzhi Ma, Rongkun Jiang, An Wang, Weijiang Wang, Hua Dang:
High-Performance Elliptic Curve Scalar Multiplication Architecture Based on Interleaved Mechanism. 757-770 - Mahipal Dargupally, Lomash Chandra Acharya, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu:
A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime. 771-779 - Donghyun Han, Sunghoon Kim, Dayoung Kim, Sungho Kang:
SPOT: Fast and Optimal Built-In Redundancy Analysis Using Smart Potential Case Collection. 780-792 - Mitchell Cooke, Nicola Nicolici:
An Embedded Architecture for DDR5 DFE Calibration Based on Channel Stimulus Inversion. 793-806 - Qian Chen, Xiaofeng Yang, Shengli Lu:
Efficient Hardware Accelerator Based on Medium Granularity Dataflow for SpTRSV. 807-820 - Pranav O. Mathews, Jennifer O. Hasler:
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems. 821-830 - Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao:
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features. 831-840 - Gustavo Aguirre, Freddy Forero, Víctor H. Champac, Michel Renovell, Florence Azaïs, Mariane Comte, Jean-Marc Gallière:
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. 841-852 - Hasan Al Shaikh, Shuvagata Saha, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, Fahim Rahman:
Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification. 853-866 - Juyong Lee, Hayoung Lee, Sooryeong Lee, Sungho Kang:
A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing. 867-871 - Hui Hu, Bingbing Yao, Yi Shan, Lei Qiu:
A Histogram-Based Calibration Algorithm of Capacitor Mismatch for SAR ADCs. 872-876 - Yongyuan Li, Xuhong Yin, Wei Guo, Qiang Wu, Yongbo Zhang, Yong You, Zhangming Zhu:
An Adaptive Maintain Power Signature (MPS) Scheme With Reusable Current Generator for Powered Device (PD). 877-881 - Letian Guo, Jincheng Zhang, Lihe Nie, Jian Wang, Yong Chen, Junyan Ren, Shunli Ma:
A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. 882-886 - Jonghyun Oh, Kwanseo Park, Young-Ha Hwang:
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces. 887-891 - Yongyuan Li, Zhuliang Li, Wei Guo, Qiang Wu, Yongbo Zhang, Yong You, Zhangming Zhu:
A Combo EMI Suppression Scheme for Multimode PSR Flyback Converter. 892-896 - Yixiao Luo, Hongzhi Liang, Zeyu Peng, Yukui Yu, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs. 897-901 - Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao:
Corrections to "GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features". 902
Volume 33, Number 4, April 2025
- Yafei Liu, Dejian Li, Zheng Yang, Chaoqin Zhang, Yunlai Zhang, Xiangyu Li, Mingwei Cao, Shouyi Yin:
A Chiplet Platform for Intelligent Radar/Sonar Leveraging Domain-Specific Reusable Active Interposer. 903-915 - Utkarsh Kumar, Sudhanshu Khanna, Ankit Mittal, Aatmesh Shrivastava:
Protecting Analog Circuits Using Switch Mode Time Domain Locking. 916-928 - Yuxin Zhang, Jueping Cai, Jizhang Chen, Lifeng Jiang, Yixin Yin:
A 285-nA Quiescent Current, 94.7% Peak Efficiency Buck Converter With AOT Control for IoT Application. 929-941 - Zixian Zheng, Wei Shu, Joseph S. Chang:
Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process. 942-952 - Anil Kali, Samrat L. Sabat, Pramod Kumar Meher:
A Flexible DA-Based Architecture for Computation of Inner Product of Variable Vectors. 953-962 - Fan Yang, Nan Li, Letian Wang, Pinfeng Jiang, Xiangshui Miao, Xingsheng Wang:
ISARA: An Island-Style Systolic Array Reconfigurable Accelerator Based on Memristors for Deep Neural Networks. 963-975 - Hao Sun, Junzhong Shen, Tian Zhang, Zhongyi Tang, Changwu Zhang, Yuhang Li, Yang Shi, Hengzhu Liu:
FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators. 976-989 - Shuai Wang, Ziwei Li, Yuang Ma, Yi Kang:
SysCIM: A Heterogeneous Chip Architecture for High-Efficiency CNN Training at Edge. 990-1003 - Yiying Liu, Minghui Yin, Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, Zhiqiang Li:
Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology. 1004-1013 - Siyu Zhang, Wendong Mao, Zhongfeng Wang:
VCNPU: An Algorithm-Hardware Co-Optimized Framework for Accelerating Neural Video Compression. 1014-1027 - Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross:
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding. 1028-1041 - Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang:
A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. 1042-1052 - Sheng Xu, Chun Li, Le Luo, Wu Zhou, Liang Yan, Xiaoming Chen:
Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators. 1053-1064 - Zhang Zhang, Zhihao Chen, Jiedong Wang, Guangjun Xie, Gang Liu:
Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing. 1065-1072 - Wenjuan Lu, Lubin Xiang, Ling Wang, Chunyu Peng, Chenghu Dai, Zhiting Lin, Xiulong Wu:
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200-237.5 TOPS/W. 1073-1081 - K. Vidyamol, Matcha Surya Prakash, Praveen Sankaran:
Efficient Pipelined Hardware Architecture for Depth-Map-Based Image Dehazing System. 1082-1093 - Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini:
FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support. 1094-1107 - Licai Hao, Lang Tian, Hao Wang, Shiyu Zhao, Qiang Zhao, Chunyu Peng, Chenghu Dai, Zhi-Ting Lin, Xiulong Wu:
A Low-Cost and Triple-Node-Upset Self-Recoverable Latch Design With Low Soft Error Rate. 1108-1117 - Jayeeta Chaudhuri, Dhruv Thapar, Arjun Chaudhuri, Farshad Firouzi, Krishnendu Chakrabarty:
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection. 1118-1131 - Chen-Yu Huang, Shi-Yu Huang:
Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test. 1132-1144 - Ziwen Xiao, Lifu Du, Zhiming Yang, Cuiyu Liu, Yang Yu:
An MIV Fault Diagnosis Method Based on Signal Transmission Performance Analysis. 1145-1156 - Yuejun Zhang, Lixun Wang, Jiawei Wang, Yongzhong Wen, Huihong Zhang, Gang Li, Pengjun Wang:
A Pay-Per-ISE RISC-V Processor With Hardware-Assisted Orthogonal Obfuscation. 1157-1161 - Shan Lu, Danyu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu:
A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS. 1162-1166 - Nuo Liu, Xiaoxian Liu, Lei Zhang, Chenhui Fan, Zhangming Zhu:
Compact On-Chip Half-Mode SIW-Based Dual-Band Bandpass Filter Using 3-D Stacked Inductors With Controllable Transmission Zero. 1167-1171 - Hanjun Zhao, Xu Yan, Hui Chu, Xiaohua Zhu, Yongxin Guo:
A 360° Tunable Phase Shifter With Low Phase Error Based on Bandpass Networks in 0.25- μm GaN Technology. 1172-1176 - Yakun Zhou, Jienan Chen, Yizhuo Zhou, Zihan Xia, Chuan Zhang, Runsheng Wang:
A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory. 1177-1181 - Kosmas Alexandridis, Giorgos Dimitrakopoulos:
Online Alignment and Addition in Multiterm Floating-Point Adders. 1182-1186 - Jiawei Cao, Chongtao Guo, Houjun Wang, Zhigang Wang, Hao Li, Geoffrey Ye Li:
Deep Learning-Based Performance Testing for Analog Integrated Circuits. 1187-1191 - Yuguo Xiang, Dayan Zhou, Minjia Song, Danfeng Zhai, Jingchao Lan, Junyan Ren, Fan Ye:
A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction. 1192-1196 - Wei Yuan, Xi Jin:
FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator. 1197-1201
Volume 33, Number 5, May 2025
- Zihan Xia, Chihun Song, Ram Krishna, Ashita Victor, Srujan Penta, Muhannad S. Bakir, Elyse Rosenbaum, Nam Sung Kim, Mingu Kang:
Exploiting Chiplet Integration Technology for Fast High-Capacity DRAM Modules. 1202-1214 - Xianrui Dou, Huaguo Liang, Zhengfeng Huang, Yingchun Lu, Tian Chen, Maoxiang Yi:
Pulse-Based Prebond TSV Testing. 1215-1223 - Jiaming Zhao, Naixin Zhou, Shibo Chen, Yijiu Zhao, Guibing Zhu:
A Model Splitting Approach to Improve Reliability and Accuracy for Alternate Test of Analog/Mixed-Signal Circuits. 1224-1234 - Germano Nicollini, Alessandro Bertolini:
A Two-Stage CMOS Amplifier With High Degree of Stability for All Capacitive Loads. 1235-1243 - Yuyang Li, Ryan Caginalp, Inhee Lee:
A Picowatt CMOS Voltage Reference Using Independent TC and Output Level Calibrations. 1244-1254 - Bo-Wei Shih, Ying-Chun Chen, Jia-Yi Lee, Woei-Luen Chen:
Complementary Voltage to Time Converter With Optimized Voltage Scaling Circuit. 1255-1263 - Seock-Hwan Noh, Seungpyo Lee, Banseok Shin, Sehun Park, Yongjoo Jang, Jaeha Kung:
All-Rounder: A Flexible AI Accelerator With Diverse Data Format Support and Morphable Structure for Multi-DNN Processing. 1264-1277 - Jianbo Guo, Tongqing Xu, Zhenyang Wu, Hao Xiao:
An Efficient Sparse CNN Inference Accelerator With Balanced Intra- and Inter-PE Workload. 1278-1291 - Yuzhou Dai, Wei Zhang, Lin Shi, Qitao Li, Zhuolun Wu, Yanyan Liu:
An Area-Efficient VLSI Architecture for High-Throughput Computation of the 2-D DWT. 1292-1303 - Melvin D. Edwards, Mohammad Alhawari:
A Laddered-Inverter Nonoverlapping Clock Generator. 1304-1313 - Keonhee Cho, Minjune Yeo, Seungjae Yei, Giseok Kim, Sangyeop Baeck, Seong-Ook Jung:
SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes. 1314-1322 - Trevor E. Pogue, Nicola Nicolici:
Strassen Multisystolic Array Hardware Architectures. 1323-1333 - Sujuan Liu, Yichen Liang, Zixing Zhang, Peiyuan Wan:
FPGA Implementation of Staged Projection Refining Multiple Orthogonal Matching Pursuit Algorithm for Compressed Sensing. 1334-1347 - Felipe Almeida, Levent Aksoy, Samuel Pagliarini:
RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking. 1348-1360 - Milad Tanavardi Nasab, Himanshu Thapliyal, Garrett S. Rose:
MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA. 1361-1372 - Qiang Zhao, Qingyi Liu, Xinyi Zhang, Licai Hao, Xin Li, Shengyue Zhang, Chunyu Peng, Zhiting Lin, Xiulong Wu:
A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening. 1373-1383 - Chenxi Chen, Jinhong Wang, Xueye Hu, Shubin Liu:
A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications. 1384-1395 - Chenghong Zhang, Dongliang Xiong, Xiaoxu Zhang, Zhengyu Wang, Huibo Gao, Kai Huang:
ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling. 1396-1406 - Zhenyang Wu, Ruichen Kan, Jianbo Guo, Hao Xiao:
Scalable and Low-Cost NTT Architecture With Conflict-Free Memory Access Scheme. 1407-1411 - Sunghae Kim, Taehee Lee, Kunhee Cho, Jaeduk Han:
A Flying-Capacitor-Assisted Single-Mode Buck-Boost Converter for Battery-Powered Applications. 1412-1416 - Pengzhou He, Tianyou Bao, Jiafeng Xie:
High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC. 1417-1421 - Tan Yee Chyan, Harikrishnan Ramiah, Sharifah Wan Muhamad Hatta, Chee-Cheow Lim, Rui Paulo Martins, Pui-In Mak, Yong Chen:
A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer. 1422-1426 - Kun Li, Hongji Fang, Zhenguo Ma, Feng Yu, Bo Zhang, Qianjian Xing:
Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform. 1427-1431 - Won Joon Choi, Myungguk Lee, Junung Choi, Jaeik Cho, Gain Kim, Byungsub Kim:
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses. 1432-1436 - Jianping Guo, Zhengping Gao, Xiaoyang Zeng, Wenhong Li, Mingyu Wang:
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver. 1437-1441 - Feng Bu, Ruixue Ding, Depeng Sun, Ge Wang, Yuan Gao, Rong Zhou, Xiaoteng Zhao, Lisheng Chen, Shubin Liu, Zhangming Zhu:
A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration. 1442-1446 - Irith Pomeranz:
Retry-Based Synchronization for Online Testing of Identical Logic Blocks. 1447-1451 - Hayoung Lee, Juyong Lee, Sungho Kang:
An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory. 1452-1456 - Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang:
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. 1457-1461 - Hossein Eslahi, Stavroula Kapoulea, Zeeshan Ali, Mohammed Waqas Mughal, Farman Ullah, Meraj Ahmad, Martin Weides, Hadi Heidari:
De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations. 1462-1466 - Shukao Dou, Zupei Gu, Heng You, Yi Zhan, Shushan Qiao, Yumei Zhou:
A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation. 1467-1471 - Yoomi Park, Sangjin Byun:
On Using nMOS-pMOS-Type Cells in a Threshold-Voltage Compensated CMOS RF-DC Rectifier. 1472-1476 - Xueyong Zhang, Yong-Jun Jo, Tony Tae-Hyoung Kim:
A 65-nm 55.8-TOPS/W Compact 2T eDRAM-Based Compute-in-Memory Macro With Linear Calibration. 1477-1481 - Seongyoon Kang, Chaehyeon Shin, Jongsun Park:
Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC. 1482-1486 - Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, Danyu Wu, Jin Wu, Xinyu Liu:
A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS. 1487-1491 - Yanbiao Liang, Huihong Shi, Zhongfeng Wang:
M2-ViT: Accelerating Hybrid Vision Transformers With Two-Level Mixed Quantization. 1492-1496 - Junyi Qian, Cai Li, Long Chen, Ruidong Li, Tuo Li, Peng Cao, Xin Si, Weiwei Shan:
An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS. 1497-1501
Volume 33, Number 6, June 2025
- Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng, Jianfei Jiang, Zhigang Mao:
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. 1502-1515 - Mahsa Zareie, Kamal El-Sankary, Dalton Martini Colombo, Ezz I. El-Masry:
A Time-Domain Frequency Analyzer Based on Goertzel Algorithm. 1516-1529 - Prajuab Pawarangkoon, Rafidah Ahmad, Ruhaifi Abdullah Zawawi, Asrulnizam Abd Manaf, Wanlop Surakampontorn, Surachoke Thanapitak:
A Nanopower EEG Low-Pass Filter Using Current-Sharing Vertical Differential Pairs. 1530-1540 - Xufeng Liao, Jiabin Wang, Peiyuan Fu, Yu Du, Lianxi Liu:
A Low-Ripple DIDO DC-DC Hybrid Interface With Optimal-Hysteresis-Controlled MPPT for TEH. 1541-1550 - Runkun Zhu, Guangyi Chen, Xueyou Shi, Bowei An, Fei Zhou, Yacong Zhang, Wengao Lu, Zhongjian Chen:
A 1-MS/s 64-Channel Data Acquisition System With Full-Scale Input Range for Area-Sensitive Application Achieved 165.3-dB FoMS/Ch. 1551-1560 - Yabo Ni, Lu Liu, Yong Zhang, Tao Zhu:
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration. 1561-1569 - Jaewon Lee, Seoyoung Jang, Yujin Choi, Donggeon Kim, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim:
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform. 1570-1581 - Jingwei Zhu, Jingguo Wu, Zongru Yang, Yu Jiang, Yun Chen:
An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing. 1582-1595 - Zihang Song, Prabodh Katti, Osvaldo Simeone, Bipin Rajendran:
Xpikeformer: Hybrid Analog-Digital Hardware Acceleration for Spiking Transformers. 1596-1609 - Mukul Lokhande, Gopal Raut, Santosh Kumar Vishvakarma:
Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads. 1610-1623 - Vuk Vranjkovic, Predrag Teodorovic, Rastislav J. R. Struharik:
Upscale Layer Acceleration on Existing AI Hardware. 1624-1637 - Yousef Safari, Adam Corbier, Dima Al Saleh, Fahad Rahman Amik, Boris Vaisband:
Thermal Simulator for Advanced Packaging and Chiplet-Based Systems. 1638-1650 - Neelam Singh, Sumit Jagdish Darak:
Enhancing Wireless PHY With Adaptive OFDM and Multiarmed Bandit Learning on Zynq System-on-Chip. 1651-1664 - Weichen Zhao, Weichen Tao, Yongheng Liu, Jingyuan Zhang, Zhongjun Zhang, Xu Yan, C. Patrick Yue, Fujiang Lin:
A 25-GHz PLL Achieving 8-ns Phase-Shifting Time With Double-Path Modulation Scheme. 1665-1678 - Yunpeng Song, Yina Lv, Wentong Li, Jialin Liu, Liang Shi:
Revisiting Multiple ECC on High-Density NAND Flash memory. 1679-1692 - Rui Xiao, Minghan Jiang, Xinran Li, Haibin Shen, Kejie Huang:
A Robust Computing-in-Memory Macro With 2T1R1C Cells and Reused Capacitors for Successive-Approximation ADC. 1693-1704 - Yifeng Song, Chenjie Liu, Rongrong Zhang, Danyang Zhu, Zhongfeng Wang:
An Efficient FPGA Implementation of Approximate Nearest Neighbor Search. 1705-1714 - Sahan Sanjaya, Aruna Jayasena, Prabhat Mishra:
Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability. 1715-1728 - Sourav Roy, Andrew Cannon, Luis de la Mata, Rabin Yu Acharya, Tasnuva Farheen, Shahin Tajik, Domenic Forte:
Sense and React: Self-Destructive Polymorphic Mechanism Against Voltage Tampered Active Physical Attacks. 1729-1742 - Yuling Shang, Longlu Geng, Chunquan Li, Zhuofan Song, Jintao Zhang, Junji Li:
An XGBoost-Based Method for Predicting the Location of MIV Open Fault. 1743-1750 - Ahmad T. Sheikh, Ali Shoker, Suhaib A. Fahmy, Paulo Esteves Veríssimo:
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips. 1751-1764 - Aibin Yan, Changli Hu, Jing Li, Na Bai, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement. 1765-1773 - Yuefei Wang, Wendong Mao, Huihong Shi, Jin Sha, Zhongfeng Wang:
An Energy-Efficient FPGA Accelerator for Swin Transformer. 1774-1778 - Wang Ye, Hanghang Gao, Zhidao Zhou, Linfang Wang, Weizeng Li, Zhi Li, Jinshan Yue, Xiaoxin Xu, Jianguo Yang, Hongyang Hu, Chunmeng Dou:
An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree. 1779-1783 - Shuyu Zhang, Menglian Zhao, Shuang Song:
A 1 mW-10 W, Over 86.4% Efficiency Tri-Mode Buck Converter With Ripple-Based Control for Mobile Applications. 1784-1788 - Ya-Rou Hsu, Aaron C.-W. Liang, Han-Ya Tsai, Yen-Ju Su, Charles H.-P. Wen, Hsuan-Ming Huang:
Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects. 1789-1793 - Le Chen, Yue Cao, Lin Ling, Shubin Liu, Haolin Han:
Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC. 1794-1798 - Javad Bagheri Asli, Alireza Saberkari, Atila Alvandpour:
A Switched-Based Slew Rate and Gain Boosting Parallel-Path Amplifier for Switched-Capacitor Applications. 1799-1802
Volume 33, Number 7, July 2025
- Andreas Tsiougkos, Vasilis F. Pavlidis:
A Design Methodology for Thermal Monitoring of Reusable Passive Interposers With RTDs. 1803-1815 - Huaguo Liang, Jiahui Xiao, Xianrui Dou, Tianming Ni, Yingchun Lu, Zhengfeng Huang:
A TSV Misalignment-Based Repair Architecture in 3-D Chips. 1816-1825 - Sanjoy Kumar Dey, Arun Kumar Barman, Pawan Sehgal, Mukul Sarkar, Shouribrata Chatterjee:
A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications. 1826-1837 - Kangkang Sun, Jingjing Liu, Feng Yan, Yuan Ren, Ruihuang Wu, Bingjun Xiong, Zhipeng Li, Jian Guan:
A 0.6-V 9.38-Bit 6.9-kS/s Capacitor-Splitting Bypass Window SAR ADC for Wearable 12-Lead ECG Acquisition Systems. 1838-1847 - Minjoon Kim, Jaehyuk So:
Real-Time Driver Monitoring: Implementing FPGA-Accelerated CNNs for Pose Detection. 1848-1857 - Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu:
DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow. 1858-1871 - Cheng Nian, Xiaorui Mo, Weiyi Zhang, Fasih Ud Din Farrukh, Yushi Guo, Fei Chen, Chun Zhang:
An 197-μJ/Frame Single-Frame Bundle Adjustment Hardware Accelerator for Mobile Visual Odometry. 1872-1885 - Heuijee Yun, Daejin Park:
S3A-NPU: A High-Performance Hardware Accelerator for Spiking Self-Supervised Learning With Dynamic Adaptive Memory Optimization. 1886-1898 - Xuchu Huang, Qingrong Huang, Zeyu Yang, Min Zhou, Zheyu Yan, Cheng Zhuo, Xunzhao Yin:
SenHDC: A 3-D NAND Flash-Based Processing-in-Sensor Hyperdimensional Computing Architecture. 1899-1909 - Junmo Lee, Minji Shon, Faaiq G. Waqar, Shimeng Yu:
3-D Digital Compute-in-Memory Benchmark With A5 CFET Technology: An Extension to Lookup-Table-Based Design. 1910-1919 - Ziyi Chen, Ioannis Savidis:
Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array. 1920-1933 - T. P. Abdul Rahoof, Vivek Chaturvedi, Mahesh Raveendranatha Panicker, Muhammad Shafique:
CapsBeam: Accelerating Capsule Network-Based Beamformer for Ultrasound Nonsteered Plane-Wave Imaging on Field-Programmable Gate Array. 1934-1944 - Kairui Sun, Meiqi Wang, Zhongfeng Wang:
RETA-AD: A Reconfigurable and Efficient Transformer Accelerator for Autonomous Driving. 1945-1958 - Leonard Puskác, Marek Benovic, Jakub Breier, Xiaolu Hou:
Make Shuffling Great Again: A Side-Channel-Resistant Fisher-Yates Algorithm for Protecting Neural Networks. 1959-1971 - Guan-Rong Chen, Kuen-Jong Lee:
A Universal Sequential Authentication Scheme for TAPC-Based Test Standards. 1972-1982 - Xiaosi Tan, Xiaohua Xie, Houren Ji, Tiancan Xia, Yongming Huang, Xiao-Hu Yu, Chuan Zhang:
A Soft Iterative Receiver With Simplified EP Detection for Coded MIMO Systems. 1994-1998 - Zewen Ye, Xin Li, Chuhui Wang, Ray C. C. Cheung, Kejie Huang:
RVSLH: Acceleration of Postquantum Standard SLH-DSA With Customized RISC-V Processor. 1999-2003 - Ehab A. Hamed, Gordy Carichner, Delbert A. Green II, Hun-Seok Kim, Inhee Lee:
Hybrid Timestamping Using Crystal and RC Oscillators for Shock-Resistant Precision. 2004-2008 - Zhiting Lin, Runru Yu, Yunhao Li, Miao Long, Yu Liu, Jianxing Zhou, Da Huo, Qingchuan Zhu, Yue Zhao, Lintao Chen, Chunyu Peng, Qiang Zhao, Xin Li, Chenghu Dai, Xiulong Wu:
A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs. 2009-2013 - Irith Pomeranz:
Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests. 2014-2018 - Jing Feng, Depeng Cheng, Xin Chen, Lei Luo, Xuwei Li, Long He, Lin Lu, Xu Wu, Xiangning Fan, Lianming Li:
A 57-71-GHz Beamforming Front-End With 6.6-dB NF and 13.9-dBm OP1 dB Using a Low-Loss Switchable Triple-Coil Transformer. 2019-2023 - Jingjing Liu, Yuxuan Huang, Weijie Ge, Wenji Mo, Yuchen Wang, Feng Yan, Kangkang Sun, Bingjun Xiong, Zhipeng Li, Jian Guan:
A 3.7-nW 248-ppm/°C Subthreshold Self-Biased CMOS Current Reference. 2024-2028 - Zhihang Qian, Shengzhe Yan, Zhuoyu Dai, Zeyu Guo, Zhaori Cong, Yifan He, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu:
An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet. 2029-2033 - Weiwei Shi, Jiasheng Wu, Yida Yuan, Zhihong Mo, Chaoyuan Wu, Jiangwei He:
An Area-Energy-Efficient 64-2048 Point FFT With Approximate Plane-Fitting Complex Multipliers. 2034-2038 - Quang Dang Truong, Phap Duong-Ngoc, Hanho Lee:
Hybrid Number Theoretic Transform Architecture for Homomorphic Encryption. 2039-2043 - Chunyu Peng, Jiating Guo, Shengyuan Yan, Yiming Wei, Xiaohang Chen, Wenjuan Lu, Chenghu Dai, Zhiting Lin, Xiulong Wu:
A 28-nm Cascode Current Mirror-Based Inconsistency-Free Charging-and-Discharging SRAM-CIM Macro for High-Efficient Convolutional Neural Networks. 2044-2048 - Ziyang Ye, Makoto Ikeda:
Implementing Homomorphic Encryption-Based Logic Locking in System-On-Chip Designs. 2049-2053 - Haikuo Shao, Zhongfeng Wang:
ASTRA: Reconfigurable Training Architecture Design for Nonlinear Softmax and Activation Functions in Transformers. 2054-2058 - Meiyu Liu, Zhijun Wang, Hanqing Luo, Shengnan Lin, Liping Liang:
A Novel High-Throughput FFT Processor With a Block-Level Pipeline for 5G MIMO OFDM Systems. 2059-2063 - Yuchuan Gong, Haojie Wei, Hongtao Guo, Jiahao Zheng, Qingyuan Hou, Zherong Liu, Teng Zhang, Jingxiao Zheng, Ye Liu, Liang Zhou, Zhengning Wang, Jun Zhou:
An Energy-Efficient Block-Based Nonmaximum Suppression Engine for High-Parallel Postprocessing of Visual Object Detection. 2064-2068 - Kunyao Lai, Enyi Yao, Zhenxing Li, Yongkui Yang:
A High-Density eDRAM Macro With Programmable Sense Amplifier and TG-Shifter for Logical-Instruction-Based In-Memory Computing. 2069-2073 - Yoochang Kim, Jun-Eun Park, Kwanseo Park, Young-Ha Hwang:
A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection. 2074-2078 - Aibin Yan, Yongkang Xu, Yue Zhang, Na Bai, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS. 2079-2083 - Taeseung Kang, Jeonghyu Yang, Eunji Song, Seungwoo Son, Hyuntae Kim, Jaeduk Han:
A 96-Gb/s 1.6-Vppd PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology. 2084-2088 - Xianrui Zhong, Guolong Fu, Yanbo Zhang, Zhangming Zhu:
A Second-Order Continuous-Time Noise-Shaping SAR ADC With Ping-Pong DACs and Gm-OTA-C Integrator. 2089-2093 - Botao Xiong, Xingyu Shao, Chang Liu, Shize Zhang, Yuchun Chang:
Design of Low-Cost and High-Accurate 8-bit Logarithmic Floating-Point Arithmetic Circuits. 2094-2098 - Ishaan Sharma, Sumit Jagdish Darak, Rohit Kumar:
High-Speed Compute-Efficient Bandit Learning for Many Arms. 2099-2103 - Saeed Aghapour, Kasra Ahmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Partial Recomputation-Based Fault Detection Approaches for Z-transform. 1983-1993
Volume 33, Number 8, August 2025
- Dongyu Xu, Wu Zhou, Zhengfeng Huang, Huaguo Liang, Xiaoqing Wen:
RHT_NoC: A Reconfigurable Hybrid Topology Architecture for Chiplet-Based Multicore System. 2104-2117 - Hanzhang Cao, Sichen Gao, Tongde Huang, Xiaolong Liu, Hao Wang, Jin Jin, Wen Wu:
A Trifilar Transformer-Based Class-F23 VCO With Noise-Circulating Technology. 2118-2131 - Ming Yan, Jaime Cardenas Chavez, Kamal El-Sankary, Li Chen, Xiaotong Lu:
A 10-bit 50-MS/s Radiation Tolerant Split Coarse/Fine SAR ADC in 65-nm CMOS. 2132-2142 - Jingjing Liu, Ruihuang Wu, Haoning Sun, Bingjun Xiong, Feng Yan, Kangkang Sun, Zhipeng Li, Jian Guan:
A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector. 2143-2152 - Jungyoun Kwak, Sunbin Deng, Junmo Lee, Suman Datta, Shimeng Yu:
Backside Active Power Delivery With Hybrid DC-DC Converter Enabled by Amorphous Oxide Semiconductor Transistors. 2153-2162 - Isa H. Altoobaji, Ahmad Hassan, Mohamed Ali, Yves Audet, Ahmed Lakhssassi:
A Compact High-Speed Capacitive Data Transfer Link With Common Mode Transient Rejection for Isolated Sensor Interfaces. 2163-2171 - Zisis Foufas, Vassilis Alimisis, Paul P. Sotiriadis:
Design of a Low-Power Analog Integrated Deep Convolutional Neural Network. 2172-2185 - Song Wang, Yixin Guo, Wei Tao, Xuerong Jia, Fujun Bai, Jie Tan, Yubing Wang, Liang Bai, Fuzhi Guo, Qi Liu, Jin Li, Peng Yin, Fenning Liu, Jing Liu, Xiaodong Long, Yanwu Han, Zhongcheng Yu, Mengzi Cheng, Song Chen, Xiping Jiang:
A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure. 2186-2199 - Qi Cao, Shang Wang, Haisheng Fu, Qifan Gao, Zhenjiao Chen, Li Gao, Feng Liang:
SC-IMC: Algorithm-Architecture Co-Optimized SRAM-Based In-Memory Computing for Sine/Cosine and Convolutional Acceleration. 2200-2213 - Xin Li, Ying Pan, Qian Jin, Lintao Chen, Yang Lou, Baofa Wu, Jiajun Long, Yongliang Zhou, Chunyu Peng, Xiulong Wu, Zhiting Lin:
Full-Array Boolean Logic CIM Macro With Self-Recycling 10T-SRAM Cell for AES Systems. 2214-2224 - Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks. 2225-2238 - Jingzhou Li, Fangfei Yu, Mingyuan Ma, Wei Liu, Yuhan Wang, Hualin Wu, Hu He:
RISC-V-Based GPGPU With Vector Capabilities for High-Performance Computing. 2239-2251 - Mingjun Cheng, Shihan Zhang, Xin Zheng, Xian Lin, Huaien Gao, Shuting Cai, Xiaoming Xiong, Bei Yu:
Efficient Design Space Exploration for the BOOM Using SAC-Based Reinforcement Learning. 2252-2263 - Chunyu Peng, Xiaohang Chen, Mengya Gao, Jiating Guo, Lijun Guan, Chenghu Dai, Zhiting Lin, Xiulong Wu:
A 28 nm Dual-Mode SRAM-CIM Macro With Local Computing Cell for CNNs and Grayscale Edge Detection. 2264-2273 - Jiaxin Qing, Philip H. W. Leong, Kin-Hong Lee, Raymond W. Yeung:
Toward High-Performance Network Coding: FPGA Acceleration With Bounded-Value Generators. 2274-2287 - Deming Wang, Ke-Xuan Chen, Guan-Jin Xu, Shun Li, Jing Wu, Yu-Xuan Huang, Jianguo Hu:
An Implementation Method for 100% ASK Modulation Applied to NFC Tags. 2288-2298 - Zhengfeng Huang, Fansheng Zeng, Yanqiao Chi, Yankun Lin, Yingchun Lu, Huaguo Liang, Jingchang Bian, Yiming Ouyang, Tianming Ni, Xiaoqing Wen:
BF PUF: A Modeling Attack-Resistant Strong PUF Based on Bent Functions. 2299-2311 - Ruikang Liu, Min Song, Changzhen Yu, Zhen Zhang, Wei Duan, Dawei Li, Ming Zhang, Meilin Wan:
A Featureless Dual-Mode Latch-Based PUF. 2312-2323 - Muhao Li, Houren Ji, Xiaosi Tan, Chuan Zhang:
Stochastic Belief Propagation-Based Iterative Detection and Decoding for MIMO Systems. 2324-2328 - Chendong Xia, Qiang Li, Zhi Li, Bing Li, Huidong Zhao, Shushan Qiao:
Accelerating Unstructured Sparse DNNs via Multilevel Partial Sum Reduction and PE Array-Level Load Balancing. 2329-2333 - Anastasios Petropoulos, Theodore Antonakopoulos:
A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations. 2334-2338 - Jun Wang, Shengzhe Yan, Xiangqu Fu, Zhihang Qian, Zhi Li, Zeyu Guo, Zhuoyu Dai, Zhaori Cong, Chunmeng Dou, Feng Zhang, Jinshan Yue, Dashan Shang:
A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. 2339-2343 - Chuanjie Chen, Xiangyu Meng, Wang Xie, Baoyong Chi:
A Sample-and-Hold-Based 453-ps True Time Delay Circuit With a Wide Bandwidth of 0.5-2.5 GHz in 65-nm CMOS. 2344-2348 - Kyungmin Baek, Jiho Kim, Kahyun Kim, Deog-Kyoon Jeong, Min-Seong Choo:
A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL. 2349-2353
Volume 33, Number 9, September 2025
- Himanshu Thapliyal, Jürgen Becker, Garrett S. Rose, Tosiron Adegbija, Selçuk Köse:
Guest Editorial: Selected Papers From IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024. 2354-2356 - Yinjie Song, Hongge Li, Xinyu Zhu, Yuhao Chen:
A Study of Signed-Digit Hybrid Stochastic Number for Arithmetic Computing. 2357-2369 - Sahar Moradi Cherati, Mohsen Barzegar, Leonel Sousa:
MSDF-Based MAC for Energy-Efficient Neural Networks. 2370-2381 - Guilherme Korol, Antonio Carlos Schneider Beck:
IoT-Edge Splitting With Pruned Early-Exit CNNs for Adaptive Inference. 2382-2394 - Muhammad Awais, Hassan Ghasemzadeh Mohammadi, Marco Platzner:
Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators. 2395-2405 - Markus Fritscher, Max Uhlmann, Philip Ostrovskyy, Daniel Reiser, Junchao Chen, Jianan Wen, Carsten Schulze, Gerhard Kahmen, Dietmar Fey, Marc Reichenbach, Milos Krstic, Christian Wenger:
RISC-V CPU Design Using RRAM-CMOS Standard Cells. 2406-2414 - Rafael da Silva, Pedro T. L. Pereira, Mateus Grellert, Ricardo Augusto da Luz Reis:
Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC. 2415-2423 - Jinming Zhang, Zhihong Chen, Yaoyao Ye, Hao Chen, Xiao Han, Jianfei Jiang, Weiguang Sheng, Ningyi Xu, Yong Lian, Guanghui He:
IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems. 2424-2437 - Farzan Rezaei, Loai G. Salem:
A Fourth-Order Tunable Bandwidth Gm-C Filter for ECG Detection Achieving -7.9 dBV IIP3 Under a 0.5 V Supply. 2438-2448 - Yishuo Meng, Jianfei Wang, Qiang Fu, Jia Hou, Siwei Xiang, Ge Li, Chen Yang:
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow. 2449-2461 - Narges Mohammadi Sarband, Oksana Moryakova, Håkan Johansson, Oscar Gustafsson:
Low-Complexity Implementation of Real-Time Reconfigurable Low-Pass Equalizers. 2462-2473 - Sin-Wei Chiu, Keshab K. Parhi:
Architectures for Serial and Parallel Pipelined NTT-Based Polynomial Modular Multiplication. 2474-2487 - Jeongmin Kim, Jaehoon Kwon, Hansol Jeong, In-Cheol Park:
Energy-Efficient Syndrome Calculation Architecture for BCH Decoders. 2488-2496 - Jincheng Wang, Yuhao Shu, Lintao Lan, Yifei Li, Bin Ning, Yuxin Zhou, Hongtu Zhang, Yajun Ha:
A 5T0C eDRAM-Based Content Addressable Memory for High-Density Searching and Logic-in-Memory. 2497-2507 - Jingyuan Qu, Debao Wei, Dejun Zhang, Yanlong Zeng, Zhelong Piao, Liyan Qiao:
IDWA: A Importance-Driven Weight Allocation Algorithm for Low Write-Verify Ratio RRAM-Based In-Memory Computing. 2508-2517 - Akul Malhotra, Sumeet Kumar Gupta:
ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory-Based Ternary LLMs. 2518-2527 - Yerui Guang, Qun Ding, Dongxu Liu:
FPGA-Oriented Design and Efficient Implementation of a Geometrically Tunable Multiscroll Conservative Chaotic System Without Equilibrium Points. 2528-2541 - Ruiqi Zhu, Houjun Wang, Susong Yang, Weikun Xie, Yindong Xiao:
Test Primitives: The Unified Notation for Characterizing March Test Sequences. 2542-2555 - Ming-Yi Lin, Wei-Kuan Chiang, Chin-Hung Wang:
Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach. 2556-2569 - Christina Dilopoulou, Yiorgos Tsiatouhas:
BTI Aging Analysis and Mitigation for Differential Input In-Memory Computing SRAMs. 2570-2579 - Na Bai, Yusheng Xia, Yaohua Xu, Yi Wang, Shaowei Wang, Xiaoqing Wen:
A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments. 2580-2591 - Kun Li, Xiangyu Hao, Zhenguo Ma, Feng Yu, Bo Zhang, Qianjian Xing:
A Fast Floating-Point Multiply-Accumulator Optimized for Sparse Linear Algebra on FPGAs. 2592-2596 - Chun-Chi Chen, Chao-Lieh Chen, Kai-Hsiang Chang:
All-Digital CMOS Pulse-Shrinking Time-to-Digital Converter With Built-in Offset-Error Cancellation and Smart Temperature Sensor. 2597-2601 - Heng Zhang, Wenhe Yin, Sunan He, Yuan Du, Li Du:
Corrections to "An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks". 2602
Volume 33, Number 10, October 2025
- Xinfei Guo:
Guest Editorial: Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2025. 2603-2605 - Tianming Ni, Hao Wu, Mu Nie, Aibin Yan, Senling Wang, Xiaoqing Wen, Jingchang Bian:
A Response-Nonlinearized DEMUX-TDC PUF for Resistance Against Modeling Attacks and Secure Authentication Protocols. 2606-2619 - Chua-Chin Wang, Pradyumna Vellanki, Jian-Jie Chen, Ralph Gerard B. Sangalang:
A 4.447 mW at 100 MHz and 49.62% Uniqueness XNOR-XOR RO PUF ASIC Using 180-nm CMOS Process for IoT Security Applications. 2620-2629 - Weiwei Shi, Haoren Qin, Jiasheng Wu, Jingbin Mai:
Design of a CNN Accelerator for Multitask EEG Signal Classification Based on RISC-V. 2630-2638 - Runye Ding, Yuyang Liu, Yujie Chen, Yao Liu, Zhiyi Yu:
A Low-Cost Secure Branch Predictor to Mitigate the Speculative Attacks by Disrupting Setup Phase. 2639-2643 - Bingjie Li, Peiyuan Wan, Zihang Zhang, Qinghua Wang, Xu Liu, Zhijie Chen, Dezhen Yang, Ming Liu, Sujuan Liu, Yongzhe Zhang:
A 45-nW 10-b 20-kS/s SAR ADC Based on Single-Capacitor Switching Scheme in 180-nm CMOS. 2644-2657 - Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yuanjin Zheng, Yong Chen:
An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier. 2658-2662 - Fei Zhou, Yuze Niu, Qingjiang Xia, Bowei An, Runkun Zhu, Wengao Lu, Yacong Zhang, Zhongjian Chen:
An Energy-Efficient Four-Channel Interface ASIC for IRFPAs With Optimized Resistor-Sharing Technique Achieving 88.1-dB SNDR. 2663-2667 - You Wu, Kei Awano, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Kiichi Niitsu:
A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage Stacking of Oscillator and Frequency Dividers for Scaling-Friendly IoTs. 2668-2679 - Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Eun-Bi Koh, Joo-Hyung Chae:
A Dual-Multiplication-Mode and Reconfigurable Digital Compute-in-Memory Macro Using Precharge-Controlled 4T1C eDRAM. 2680-2689 - Yangyi Zhang, Xianglong Wang, Lei Chen, Fengwei An:
ReHIT: Reconfigurable High-Radix Iterative-Taylor Architecture for Ultraprecise Logarithm/Exponential Functions in FPGA-Based Softmax Accelerators. 2690-2701 - Yujie Chen, Chen Yang, Yuheng Xia, Yishuo Meng, Jianfei Wang, Qiang Fu, Li Geng:
RTA: A Reconfigurable Transformer Accelerator Exploiting Sparsity via Low-Bit-Width Prediction. 2702-2714 - Zhechen Yuan, Binzhe Yuan, Chaolin Rao, Yiren Zhu, Yunxiang He, Pingqiang Zhou, Jingyi Yu, Xin Lou:
A Neural Rendering Coprocessor With Optimized Ray Representation and Marching. 2715-2727 - Jinyu Gao, Ye Zhao, Ziyuan Wang, Long Chen, Aoming Zhan, Qihang Jiang, Feng Zhang, Yong Chen, Shushan Qiao:
A General-Purpose Computing Core With Cooperative Motion Detection and Feature Extraction for Always-On PWM Image Sensors. 2728-2739 - Xinyue Gu, Jiahe Li, Shiyv Wu, Hongming Lyu:
A 1.28-μW Heart-Rate SoC Achieving 99.68% QRS Detection Accuracy for Long-Term Continuous Cardiac Monitoring Applications. 2740-2748 - Yang Min, Nan Qi, Yihan Chen, Yi Zhang, Minye Zhu, Guike Li, Yonghui Lin, Huiyao Peng, Mo Guang, Kaiwen Long, Zhao Zhang, Jian Liu, Nanjian Wu, Jingbo Shi, Yong Chen, Frank F. Shi, Liyuan Liu:
A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS. 2749-2760 - Wei Zhang, Yiwei Luo, Xianglong Wang, Jiaqi Ouyang, Lei Chen, Fengwei An:
Dual-Thread Deflate/Inflate Accelerator With Multicheckpoint Control With High Throughput and Compression Ratio for Bandwidth-Efficient Systems. 2761-2771 - Lishuo Deng, Junyi Qian, Zhengguo Shen, Cai Li, Jingchen Wang, Zhangrui Qian, Ziyu Li, Longning Qi, Weiwei Shan:
A Compound Timing Detection of Both Data Transition and Path Activation for Reliable In Situ Error Detection and Correction. 2772-2782 - Aibin Yan, Jiajia Zhang, Xiumin Xu, Hanxiang Li, Na Bai, Zhengfeng Huang, Xiaolei Wang, Xiaoqing Wen, Patrick Girard:
TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications. 2783-2794 - Weiwei Shi, Xiaocong Cao, Zhuoliang Zou, Yuping Gao, Jiasheng Wu:
Hybrid Approximate Multipliers With Merits Balance for Digital Processing and Neural Networks. 2795-2805 - Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua:
Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers. 2806-2814 - Alireza Mosalmani, Yasser Rezaeiyan, Simon Richter, Milad Zamani, Yarallah Koolivand, Farshad Moradi:
A 0.97 nJ/Conversion BJT-Based Temperature Sensor With a Low-Power Two-Stage Dynamic Comparator. 2815-2823 - Wendi Sun, Yifan Wang, Xu Cao, Yao Ge, Song Chen, Yi Kang:
Comma: A Communication-Minimized Model-Architecture Framework for Efficient Convolution Acceleration. 2824-2837 - Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Kentaro Yoshioka:
ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits. 2838-2851 - Kari Hepola, Tharaka Ranasinghe Arachchige, Joonas Multanen, Pekka Jääskeläinen:
Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions. 2852-2861 - Sebastian Haas, Christopher Dunkel, Friedrich Pauls, Mattis Hasler, Yogesh Verma, Nilanjana Das, Michael Raitza:
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing. 2862-2872 - Kevin Vicuña, Massimo Vatalaro, Frédéric Amiel, Felice Crupi, Lionel Trojman:
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications. 2873-2882 - Jiayu Liu, Yuanhang Li, Zhengyang Huang, Chao Chen, Ruiqi Chen, Bruno da Silva:
FASE: An FPGA-Based Accelerator for Lightweight Sample Entropy With Monte Carlo Sampling. 2883-2896 - Xie He, Dongxu Li:
A 3-bit/Unit Time-Domain Compute-In-Memory Macro With Adjustable Unit Delay. 2897-2901 - Ming-Yi Lin, Wei-Kuan Chiang, Chin-Hung Wang:
Corrections to "Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach". 2902
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