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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 33
Volume 33, Number 1, January 2025
- Hyoseok Song
, Kwangmin Kim, Gain Kim, Byungsub Kim:
A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization. 1-9 - Jie Ding, Fuming Liu, Kuan Deng, Zihan Zheng, Jingnan Zheng, Yongzhen Chen, Jiangfeng Wu:
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration. 10-20 - Haitao Du, Hairui Zhu, Song Chen, Yi Kang:
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling. 21-34 - Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai:
A 0.05-1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications. 35-46 - Yu Liu, Yupeng Shen, Mingliang Chen, Hui Xu, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu:
A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC. 47-51 - Tianzhu Xiong, Yuyang Ye, Xin Si, Jun Yang:
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. 52-65 - Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego:
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators. 66-74 - Seung-Hwan Bae, Hyuk-Jae Lee, Hyun Kim:
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution. 75-87 - Jie Li, Chuanlun Zhang, Wenxuan Yang, Heng Li, Xiaoyan Wang, Chuanjun Zhao, Shuangli Du, Yiguang Liu:
FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation. 88-101 - Zhichao Chen, Ali H. Hassan, Rhesa Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta:
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. 102-113 - Anawin Opasatian, Makoto Ikeda:
Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier. 114-127 - Ken Li, Tian Xie, Tzu-Han Wang, Shaolan Li:
VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator. 128-139 - Tianning Gao, Yifan Wang, Ming Zhu, Xiulong Wu, Dian Zhou, Zhaori Bi:
An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. 140-153 - Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu:
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. 154-167 - Jhe-En Lin, Shen-Iuan Liu:
A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE. 168-178 - Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam:
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory. 179-192 - Dongkwun Kim, Zhaoqing Wang, Paul Xuanyuanliang Huang, Pavan Kumar Chundi, Suhwan Kim, Andres A. Blanco, Ram K. Krishnamurthy, Mingoo Seok:
A 4.2-to-0.5-V, 0.8-μA-0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor. 193-206 - Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. 207-220 - Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang:
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V. 221-233 - Zhaolin Yang, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. 234-247 - Shuming Guo, Yinyin Lin, Hao Wang, Yao Li, Chongyan Gu, Weiqiang Liu, Yijun Cui:
A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications. 248-260 - Xingye Liu, Paul Ampadu:
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation. 261-274 - Alexandre Almeida da Silva, Lucas Nogueira, Alexandre Coelho, Jarbas A. N. Silveira, César A. M. Marcon:
Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically-Partially Connected 3D-NoC. 275-287 - Lakshmi Bhanuprakash Reddy Konduru, Vikramkumar Pudi, Balasubramanyam Appina:
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. 288-292 - Zhihao Zhou, Wei Zhang, Xinyi Guo, Jianhan Zhao, Yanyan Liu:
High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes. 293-297 - Yiwei Chang, Zhichuan Guo:
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks. 298-302
Volume 33, Number 2, February 2025
- Zhan Qu, Zhenjiao Chen, Xingqiang Shi, Ya Zhao, Guohe Zhang, Feng Liang:
Multiobjective Optimization of Class-F Oscillators. 303-314 - Shiro Dosho, Ludovico Minati, Kazuki Maari, Shungo Ohkubo, Hiroyuki Ito:
A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier. 315-325 - Chiara Venezia, Andrea Ballo, Alfio Dario Grasso, Alessandro Rizzo, Calogero Ribellino, Salvatore Pennisi:
46-nA High-PSR CMOS Buffered Voltage Reference With 1.2-5 V and -40 ◦C to 125 ◦C Operating Range. 326-336 - Ebenezer C. Usih, Naimul Hassan, Alexander J. Edwards, Felipe García-Sánchez, Pedram Khalili Amiri, Joseph S. Friedman:
Toggle SOT-MRAM Architecture With Self-Terminating Write Operation. 337-345 - Sudipta Das, Samuel Riedel, Mohamed Naeim, Moritz Brunion, Marco Bertuletti, Luca Benini, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic:
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. 346-357 - Gauthaman Murali, Min Gyu Park, Sung Kyu Lim:
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators. 358-370 - Lixun Wang, Yuejun Zhang, Pengjun Wang, Jianguo Yang, Huihong Zhang, Gang Li, Qikang Li:
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices. 371-383 - Tiancheng Cao, Weihao Yu, Yuan Gao, Chen Liu, Tantan Zhang, Shuicheng Yan, Wang Ling Goh:
Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications. 384-394 - Shushi Chen, Leilei Huang, Zhao Zan, Xiaoyang Zeng, Yibo Fan:
An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC. 395-407 - Yazheng Tu, Shi Bai, Jinjun Xiong, Jiafeng Xie:
SCOPE: Schoolbook-Originated Novel Polynomial Multiplication Accelerators for NTRU-Based PQC. 408-420 - Ruichang Jiang, Wenbin Ye:
Hardware-Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA. 421-434 - Chao Ji, Xiaohu You, Chuan Zhang, Christoph Studer:
Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation. 435-448 - Ruijun Ma, Stefan Holst, Hui Xu, Xiaoqing Wen, Senling Wang, Jiuqi Li, Aibin Yan:
Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. 449-461 - Seung Ho Shin, Hayoung Lee, Sungho Kang:
Effective Parallel Redundancy Analysis Using GPU for Memory Repair. 462-474 - Shuo Cai, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu:
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications. 475-487 - Youngki Moon, Seung Ho Shin, Seokjun Jang, Duyeon Won, Sungho Kang:
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM. 488-498 - Huarun Chen, Yijun Liu, Wujian Ye, Jialiang Ye, Yuehai Chen, Shaozhen Chen, Chao Han:
Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform. 499-511 - Zhiquan Wan, Zhipeng Cao, Shunbin Li, Peijie Li, Qingwen Deng, Weihao Wang, Kun Zhang, Guandong Liu, Ruyun Zhang, Qinrang Liu:
Architectural Exploration for Waferscale Switching System. 512-524 - Yuanbo Wang, Liang Chang, Jingke Wang, Pan Zhao, Jiahao Zeng, Xin Zhao, Wuyang Hao, Liang Zhou, Haining Tan, Yinhe Han, Jun Zhou:
PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique. 525-536 - Akhil Reddy Pakala, Zhiyu Chen, Kaiyuan Yang:
MBSNTT: A Highly Parallel Digital In-Memory Bit-Serial Number Theoretic Transform Accelerator. 537-545 - Jia-Li Duan, Chi Zhang, Li-Hui Wang, Lei Shen:
SMBHA: A System-Level Multicore BGV Hardware Accelerator Based on FPGA. 546-557 - Pedro Tauã Lopes Pereira, Patrícia Ücker Leleu da Costa, Eduardo A. C. da Costa, Paulo F. Flores, Sergio Bampi:
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers. 558-562 - Dingyang Zou, Gaoche Zhang, Xu Zhang, Meiqi Wang, Zhongfeng Wang:
An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators. 563-567 - Wanbin Zha, Jiangtao Xu, Kaiming Nie, Zhiyuan Gao:
A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors. 568-572 - Yuxin Ji, Yuhang Zhang, Changyan Chen, Jian Zhao, Fakhrul Zaman Rokhani, Yehea Ismail, Yongfu Li:
A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI. 573-577 - Chenjia Xie, Zhuang Shao, Ning Zhao, Xingyuan Hu, Yuan Du, Li Du:
A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations. 578-582 - Quanzhen Liang, Xiao Wang, Kuisong Wang, Yuepeng Yan, Xiaoxin Liang:
Analysis and Design of Wideband GaAs Digital Step Attenuators. 583-587 - Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang:
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. 588-592 - Jiliang Liu, Huidong Zhao, Zhi Li, Kangning Wang, Shushan Qiao:
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit. 593-597 - Jahyun Koo, Hyunwoo Son, Jae-Yoon Sim:
A 9.6-nW Wake-Up Timer With RC-Referenced Subharmonic Locking Using Dual Leakage-Based Oscillators. 598-602
Volume 33, Number 3, March 2025
- Mircea R. Stan:
Editorial: Renewed Excellence for 2025-2026. 603-626 - Changle Zhi, Gang Dong, Deguang Yang, Daihang Liu, Yinghao Feng, Yang Wang, Zhangming Zhu:
Electrical and Thermal Characteristics Optimization in Interposer-Based 2.5-D Integrated Circuits. 627-637 - Felix Burkhardt, Florian Protze, Frank Ellinger:
A Single-Ended High-Voltage-Compliant 11-bit Current-Steering Digital-to-Analog Converter for Adaptive Noise Cancellation in Power Over Data Line Networks. 638-650 - Yuhong Lu, Ting-An Yen, Rakshit Dambe Nayak, Shashank Alevoor, Bhushan Talele, Spoorti Patil, Keith Kunz, Bertan Bakkaloglu:
A Novel Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR nMOS LDOs. 651-661 - Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Taehwan Kim, Chulwoo Kim:
A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. 662-672 - Yechen Tian, Yutong Zhang, Junjie Gu, Hao Xu, Weitian Liu, Rui Yin, Zongming Duan, Hao Gao, Na Yan:
Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver. 673-684 - Weihao Wang, Kong-Pang Pun:
An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop. 685-696 - Srishti Agrawal, Rakesh Kumar Palani, Sweta Tripathi:
Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars. 697-706 - Zhaoteng Meng, Lin Shu, Jianing Zeng, Zhan Li, Kailin Lv, Haoyue Yang, Jie Hao:
MASL-AFU: A High Memory Access Efficiency 2-D Scalable LUT-Based Activation Function Unit for On-Device DNN Training. 707-719 - Yong-Tai Chen, Yen-Ting Chiu, Hao-Jiun Tu, Chao-Tsung Huang:
Falcon: A Fused-Layer Accelerator With Layer-Wise Hybrid Inference Flow for Computational Imaging CNNs. 720-732 - Eduardo Antonio Cesar da Costa, Morgana Macedo Azevedo da Rosa:
RCU- 2m: A VLSI Radix- 2m Cubic Unit. 733-745 - Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Hideharu Amano, Tohru Mogami, Yoshio Mita, Makoto Ikeda, Tadahiro Kuroda:
Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication. 746-756 - Jingqi Zhang, Zhiming Chen, Mingzhi Ma, Rongkun Jiang, An Wang, Weijiang Wang, Hua Dang:
High-Performance Elliptic Curve Scalar Multiplication Architecture Based on Interleaved Mechanism. 757-770 - Mahipal Dargupally, Lomash Chandra Acharya, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu:
A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime. 771-779 - Donghyun Han, Sunghoon Kim, Dayoung Kim, Sungho Kang:
SPOT: Fast and Optimal Built-In Redundancy Analysis Using Smart Potential Case Collection. 780-792 - Mitchell Cooke, Nicola Nicolici:
An Embedded Architecture for DDR5 DFE Calibration Based on Channel Stimulus Inversion. 793-806 - Qian Chen, Xiaofeng Yang, Shengli Lu:
Efficient Hardware Accelerator Based on Medium Granularity Dataflow for SpTRSV. 807-820 - Pranav O. Mathews, Jennifer O. Hasler:
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems. 821-830 - Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao:
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features. 831-840 - Gustavo Aguirre, Freddy Forero, Víctor H. Champac, Michel Renovell, Florence Azaïs, Mariane Comte, Jean-Marc Gallière:
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. 841-852 - Hasan Al Shaikh, Shuvagata Saha, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification. 853-866 - Juyong Lee, Hayoung Lee, Sooryeong Lee, Sungho Kang:
A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing. 867-871 - Hui Hu, Bingbing Yao, Yi Shan, Lei Qiu:
A Histogram-Based Calibration Algorithm of Capacitor Mismatch for SAR ADCs. 872-876 - Yongyuan Li, Xuhong Yin, Wei Guo, Qiang Wu, Yongbo Zhang, Yong You, Zhangming Zhu:
An Adaptive Maintain Power Signature (MPS) Scheme With Reusable Current Generator for Powered Device (PD). 877-881 - Letian Guo, Jincheng Zhang, Lihe Nie, Jian Wang, Yong Chen, Junyan Ren, Shunli Ma:
A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. 882-886 - Jonghyun Oh, Kwanseo Park, Young-Ha Hwang:
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces. 887-891 - Yongyuan Li, Zhuliang Li, Wei Guo, Qiang Wu, Yongbo Zhang, Yong You, Zhangming Zhu:
A Combo EMI Suppression Scheme for Multimode PSR Flyback Converter. 892-896 - Yixiao Luo, Hongzhi Liang, Zeyu Peng, Yukui Yu, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs. 897-901 - Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao:
Corrections to "GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features". 902
Volume 33, Number 4, April 2025
- Yafei Liu, Dejian Li, Zheng Yang, Chaoqin Zhang, Yunlai Zhang, Xiangyu Li, Mingwei Cao, Shouyi Yin:
A Chiplet Platform for Intelligent Radar/Sonar Leveraging Domain-Specific Reusable Active Interposer. 903-915 - Utkarsh Kumar, Sudhanshu Khanna, Ankit Mittal, Aatmesh Shrivastava:
Protecting Analog Circuits Using Switch Mode Time Domain Locking. 916-928 - Yuxin Zhang, Jueping Cai, Jizhang Chen, Lifeng Jiang, Yixin Yin:
A 285-nA Quiescent Current, 94.7% Peak Efficiency Buck Converter With AOT Control for IoT Application. 929-941 - Zixian Zheng, Wei Shu, Joseph S. Chang:
Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process. 942-952 - Anil Kali, Samrat L. Sabat, Pramod Kumar Meher:
A Flexible DA-Based Architecture for Computation of Inner Product of Variable Vectors. 953-962 - Fan Yang, Nan Li, Letian Wang, Pinfeng Jiang, Xiangshui Miao, Xingsheng Wang:
ISARA: An Island-Style Systolic Array Reconfigurable Accelerator Based on Memristors for Deep Neural Networks. 963-975 - Hao Sun, Junzhong Shen, Tian Zhang, Zhongyi Tang, Changwu Zhang, Yuhang Li, Yang Shi, Hengzhu Liu:
FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators. 976-989 - Shuai Wang, Ziwei Li, Yuang Ma, Yi Kang:
SysCIM: A Heterogeneous Chip Architecture for High-Efficiency CNN Training at Edge. 990-1003 - Yiying Liu, Minghui Yin, Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, Zhiqiang Li:
Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology. 1004-1013 - Siyu Zhang, Wendong Mao, Zhongfeng Wang:
VCNPU: An Algorithm-Hardware Co-Optimized Framework for Accelerating Neural Video Compression. 1014-1027 - Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross:
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding. 1028-1041 - Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang:
A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. 1042-1052 - Sheng Xu, Chun Li, Le Luo, Wu Zhou, Liang Yan, Xiaoming Chen:
Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators. 1053-1064 - Zhang Zhang, Zhihao Chen, Jiedong Wang, Guangjun Xie, Gang Liu:
Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing. 1065-1072 - Wenjuan Lu, Lubin Xiang, Ling Wang, Chunyu Peng, Chenghu Dai, Zhiting Lin, Xiulong Wu:
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200-237.5 TOPS/W. 1073-1081 - K. Vidyamol, Matcha Surya Prakash, Praveen Sankaran:
Efficient Pipelined Hardware Architecture for Depth-Map-Based Image Dehazing System. 1082-1093 - Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini:
FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support. 1094-1107 - Licai Hao, Lang Tian, Hao Wang, Shiyu Zhao, Qiang Zhao, Chunyu Peng, Chenghu Dai, Zhi-Ting Lin, Xiulong Wu:
A Low-Cost and Triple-Node-Upset Self-Recoverable Latch Design With Low Soft Error Rate. 1108-1117 - Jayeeta Chaudhuri, Dhruv Thapar, Arjun Chaudhuri, Farshad Firouzi, Krishnendu Chakrabarty:
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection. 1118-1131 - Chen-Yu Huang, Shi-Yu Huang:
Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test. 1132-1144 - Ziwen Xiao, Lifu Du, Zhiming Yang, Cuiyu Liu, Yang Yu:
An MIV Fault Diagnosis Method Based on Signal Transmission Performance Analysis. 1145-1156 - Yuejun Zhang, Lixun Wang, Jiawei Wang, Yongzhong Wen, Huihong Zhang, Gang Li, Pengjun Wang:
A Pay-Per-ISE RISC-V Processor With Hardware-Assisted Orthogonal Obfuscation. 1157-1161 - Shan Lu, Danyu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu:
A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS. 1162-1166 - Nuo Liu, Xiaoxian Liu, Lei Zhang, Chenhui Fan, Zhangming Zhu:
Compact On-Chip Half-Mode SIW-Based Dual-Band Bandpass Filter Using 3-D Stacked Inductors With Controllable Transmission Zero. 1167-1171 - Hanjun Zhao, Xu Yan, Hui Chu, Xiaohua Zhu, Yongxin Guo:
A 360° Tunable Phase Shifter With Low Phase Error Based on Bandpass Networks in 0.25- μm GaN Technology. 1172-1176 - Yakun Zhou, Jienan Chen, Yizhuo Zhou, Zihan Xia, Chuan Zhang, Runsheng Wang:
A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory. 1177-1181 - Kosmas Alexandridis, Giorgos Dimitrakopoulos:
Online Alignment and Addition in Multiterm Floating-Point Adders. 1182-1186 - Jiawei Cao, Chongtao Guo, Houjun Wang, Zhigang Wang, Hao Li, Geoffrey Ye Li:
Deep Learning-Based Performance Testing for Analog Integrated Circuits. 1187-1191 - Yuguo Xiang, Dayan Zhou, Minjia Song, Danfeng Zhai, Jingchao Lan, Junyan Ren, Fan Ye:
A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction. 1192-1196 - Wei Yuan, Xi Jin:
FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator. 1197-1201
Volume 33, Number 5, May 2025
- Zihan Xia, Chihun Song, Ram Krishna, Ashita Victor, Srujan Penta, Muhannad S. Bakir, Elyse Rosenbaum, Nam Sung Kim, Mingu Kang:
Exploiting Chiplet Integration Technology for Fast High-Capacity DRAM Modules. 1202-1214 - Xianrui Dou, Huaguo Liang, Zhengfeng Huang, Yingchun Lu, Tian Chen, Maoxiang Yi:
Pulse-Based Prebond TSV Testing. 1215-1223 - Jiaming Zhao, Naixin Zhou, Shibo Chen, Yijiu Zhao, Guibing Zhu:
A Model Splitting Approach to Improve Reliability and Accuracy for Alternate Test of Analog/Mixed-Signal Circuits. 1224-1234 - Germano Nicollini, Alessandro Bertolini:
A Two-Stage CMOS Amplifier With High Degree of Stability for All Capacitive Loads. 1235-1243 - Yuyang Li, Ryan Caginalp, Inhee Lee:
A Picowatt CMOS Voltage Reference Using Independent TC and Output Level Calibrations. 1244-1254 - Bo-Wei Shih, Ying-Chun Chen, Jia-Yi Lee, Woei-Luen Chen:
Complementary Voltage to Time Converter With Optimized Voltage Scaling Circuit. 1255-1263 - Seock-Hwan Noh, Seungpyo Lee, Banseok Shin, Sehun Park, Yongjoo Jang, Jaeha Kung:
All-Rounder: A Flexible AI Accelerator With Diverse Data Format Support and Morphable Structure for Multi-DNN Processing. 1264-1277 - Jianbo Guo, Tongqing Xu, Zhenyang Wu, Hao Xiao:
An Efficient Sparse CNN Inference Accelerator With Balanced Intra- and Inter-PE Workload. 1278-1291 - Yuzhou Dai, Wei Zhang, Lin Shi, Qitao Li, Zhuolun Wu, Yanyan Liu:
An Area-Efficient VLSI Architecture for High-Throughput Computation of the 2-D DWT. 1292-1303 - Melvin D. Edwards, Mohammad Alhawari:
A Laddered-Inverter Nonoverlapping Clock Generator. 1304-1313 - Keonhee Cho, Minjune Yeo, Seungjae Yei, Giseok Kim, Sangyeop Baeck, Seong-Ook Jung:
SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes. 1314-1322 - Trevor E. Pogue, Nicola Nicolici:
Strassen Multisystolic Array Hardware Architectures. 1323-1333 - Sujuan Liu, Yichen Liang, Zixing Zhang, Peiyuan Wan:
FPGA Implementation of Staged Projection Refining Multiple Orthogonal Matching Pursuit Algorithm for Compressed Sensing. 1334-1347 - Felipe Almeida, Levent Aksoy, Samuel Pagliarini:
RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking. 1348-1360 - Milad Tanavardi Nasab, Himanshu Thapliyal, Garrett S. Rose:
MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA. 1361-1372 - Qiang Zhao, Qingyi Liu, Xinyi Zhang, Licai Hao, Xin Li, Shengyue Zhang, Chunyu Peng, Zhiting Lin, Xiulong Wu:
A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening. 1373-1383 - Chenxi Chen, Jinhong Wang, Xueye Hu, Shubin Liu:
A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications. 1384-1395 - Chenghong Zhang, Dongliang Xiong, Xiaoxu Zhang, Zhengyu Wang, Huibo Gao, Kai Huang:
ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling. 1396-1406 - Zhenyang Wu, Ruichen Kan, Jianbo Guo, Hao Xiao:
Scalable and Low-Cost NTT Architecture With Conflict-Free Memory Access Scheme. 1407-1411 - Sunghae Kim, Taehee Lee, Kunhee Cho, Jaeduk Han:
A Flying-Capacitor-Assisted Single-Mode Buck-Boost Converter for Battery-Powered Applications. 1412-1416 - Pengzhou He, Tianyou Bao, Jiafeng Xie:
High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC. 1417-1421 - Tan Yee Chyan, Harikrishnan Ramiah, Sharifah Wan Muhamad Hatta, Chee-Cheow Lim, Rui Paulo Martins, Pui-In Mak, Yong Chen:
A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer. 1422-1426 - Kun Li, Hongji Fang, Zhenguo Ma, Feng Yu, Bo Zhang, Qianjian Xing:
Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform. 1427-1431 - Won Joon Choi, Myungguk Lee, Junung Choi, Jaeik Cho, Gain Kim, Byungsub Kim:
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses. 1432-1436 - Jianping Guo, Zhengping Gao, Xiaoyang Zeng, Wenhong Li, Mingyu Wang:
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver. 1437-1441 - Feng Bu, Ruixue Ding, Depeng Sun, Ge Wang, Yuan Gao, Rong Zhou, Xiaoteng Zhao, Lisheng Chen, Shubin Liu, Zhangming Zhu:
A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration. 1442-1446 - Irith Pomeranz:
Retry-Based Synchronization for Online Testing of Identical Logic Blocks. 1447-1451 - Hayoung Lee, Juyong Lee, Sungho Kang:
An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory. 1452-1456 - Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang:
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. 1457-1461 - Hossein Eslahi, Stavroula Kapoulea, Zeeshan Ali, Mohammed Waqas Mughal, Farman Ullah, Meraj Ahmad, Martin Weides, Hadi Heidari:
De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations. 1462-1466 - Shukao Dou, Zupei Gu, Heng You, Yi Zhan, Shushan Qiao, Yumei Zhou:
A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation. 1467-1471 - Yoomi Park, Sangjin Byun:
On Using nMOS-pMOS-Type Cells in a Threshold-Voltage Compensated CMOS RF-DC Rectifier. 1472-1476 - Xueyong Zhang, Yong-Jun Jo, Tony Tae-Hyoung Kim:
A 65-nm 55.8-TOPS/W Compact 2T eDRAM-Based Compute-in-Memory Macro With Linear Calibration. 1477-1481 - Seongyoon Kang, Chaehyeon Shin, Jongsun Park:
Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC. 1482-1486 - Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, Danyu Wu, Jin Wu, Xinyu Liu:
A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS. 1487-1491 - Yanbiao Liang, Huihong Shi, Zhongfeng Wang:
M2-ViT: Accelerating Hybrid Vision Transformers With Two-Level Mixed Quantization. 1492-1496 - Junyi Qian, Cai Li, Long Chen, Ruidong Li, Tuo Li, Peng Cao, Xin Si, Weiwei Shan:
An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS. 1497-1501
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