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ORCIDLu Jie 0001
Person information
- affiliation: Tsinghua University, Department of Electronic Engineering, Beijing, China
- affiliation (PhD 2021): University of Michigan, Department of Electrical and Computer Engineering, Ann Arbor, MI, USA
- affiliation (former): Zhejiang University, Hangzhou, Zhejiang, China
Other persons with the same name
- Lu Jie 0002 — Anhui Agricultural University, College of Information and Computer Science, Hefei, China
- Lu Jie 0003 — Sun Yat-sen University, School of Intelligent Systems Engineering, Shenzhen, China
- Lu Jie 0004 — LLM-jp
- Jie Lu 0006
![[0000-0002-6831-7413]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-6831-7413")
(aka: Lu Jie 0006) — National Digital Switching System Engineering and Technological Research and Development Center, Zhengzhou, China (and 2 more)
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2020 – today
- 2024
[j8]Mingtao Zhan, Lu Jie, Xiyuan Tang, Yi Zhong, Nan Sun:
A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp. IEEE J. Solid State Circuits 59(7): 2209-2218 (2024)- [c21]Yunsong Tao, Yi Zhong, Jin Shao, Changyou Men, Lu Jie, Nan Sun:
A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs. ISCAS 2024: 1-5 - [c20]Xiyu He, Mingyang Gu, Hanjun Jiang, Yi Zhong, Nan Sun, Lu Jie:
9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs. ISSCC 2024: 172-174 - [c19]Yunsong Tao, Mingyang Gu, Baoyong Chi, Yi Zhong, Lu Jie, Nan Sun:
22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration. ISSCC 2024: 394-396 - 2023
- [j7]Mingtao Zhan, Lu Jie, Yi Zhong, Nan Sun:
A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor. IEEE J. Solid State Circuits 58(12): 3576-3585 (2023) - [c18]Zhishuai Zhang, Zijie Gao, Siyu Huang, Nan Sun, Lu Jie:
A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking. CICC 2023: 1-2 - [c17]Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun:
An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. CICC 2023: 1-2 - [c16]Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun:
A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration. ESSCIRC 2023: 145-148 - [c15]Chaoyang Xing, Yi Zhong, Nan Sun, Lu Jie:
A 0.021mm2 92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2nd-order RT-DEM and Quiet Chopping. ESSCIRC 2023: 293-296 - [c14]Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun:
A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors. ESSCIRC 2023: 329-332 - [c13]Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang:
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC 2023: 176-177 - [c12]Mingtao Zhan, Lu Jie, Nan Sun:
A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. ISSCC 2023: 272-273 - [c11]Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu:
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c10]Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun:
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. CICC 2022: 1-2 - [c9]Yunsong Tao, Kareem Ragab, Jin Shao, Pengpeng Chen, Yi Zhong, Lu Jie, Nan Sun:
A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs. ISCAS 2022: 21-25 - [c8]Chaoyang Xing, Yi Zhong, Jin Shao, Pengpeng Chen, Lu Jie, Nan Sun:
A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation. ISCAS 2022: 3215-3218 - [c7]Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun:
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. ISSCC 2022: 1-3 - [c6]Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun:
A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp. ISSCC 2022: 164-166 - [c5]Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn:
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits 2022: 264-265 - 2021
- [j6]Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn:
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. IEEE J. Solid State Circuits 56(12): 3681-3693 (2021) - [c4]Boyi Zheng, Lu Jie, Michael P. Flynn:
TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. ESSCIRC 2021: 511-514 - [c3]Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn:
10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. ISSCC 2021: 167-169 - 2020
- [j5]Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Michael P. Flynn:
A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension. IEEE J. Solid State Circuits 55(12): 3236-3247 (2020) - [c2]Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Runyu Wang, Michael P. Flynn:
9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth. ISSCC 2020: 160-162
2010 – 2019
- 2019
- [j4]Daniel Weyer, Mehmet Batuhan Dayanik, Lu Jie, Ahmed Albalawi, Abdulhamed Alothaimen, Mohammed Aseeri, Michael P. Flynn:
Design Considerations for Integrated Radar Chirp Synthesizers. IEEE Access 7: 13723-13736 (2019) - [j3]Lu Jie, Boyi Zheng, Michael P. Flynn:
A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC. IEEE J. Solid State Circuits 54(12): 3386-3395 (2019) - [c1]Lu Jie, Boyi Zheng, Michael P. Flynn:
A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC. ISSCC 2019: 332-334 - 2018
- [j2]Nicholas Collins, Andres Tamez, Lu Jie, Jorge Pernillo, Michael P. Flynn:
A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1589-1593 (2018) - 2017
- [j1]Qian Zhou, Yan Han, Shifeng Zhang, Xiaoxia Han, Lu Jie, Ray C. C. Cheung, Guangtao Feng:
A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process. Sci. China Inf. Sci. 60(8): 89401 (2017)
Coauthor Index
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