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ORCIDWei Tang 0010
Person information
- affiliation (PhD 2019): University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA
Other persons with the same name
- Wei Tang — disambiguation page
- Wei Tang 0001 — Google Inc, New York, NY, USA (and 2 more)
- Wei Tang 0002
![[0000-0003-1925-0782]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0003-1925-0782")
— New Mexico State University, Las Cruces, NM, USA (and 1 more) - Wei Tang 0003 — Northwestern Polytechnical University, School of Automation, Xi'an, China
- Wei Tang 0004 — Indiana University Bloomington, IN, USA (and 4 more)
- Wei Tang 0005 — Virginia Tech, Blacksburg, VA, USA
- Wei Tang 0006 — Georgia Institute of Technology, Atlanta, GA, USA
- Wei Tang 0007 — Shanghai Jiao Tong University, Department of Electronic Engineering, China
- Wei Tang 0008 — China University of Mining and Technology, College of Geoscience and Surveying Engineering, Beijing, China (and 1 more)
- Wei Tang 0009 — China Agricultural University, College of Information and Electrical Engineering, Beijing, China (and 1 more)
- Wei Tang 0011 — Jiangsu University, School of Computer Science and Communication Engineering, Zhenjiang, China
- Wei Tang 0012 — Army Engineering University of PLA, Command and Control Engineering College, Nanjing, China
- Wei Tang 0013 — Beijing University of Posts and Telecommunications, Beijing, China
- Wei Tang 0014 — University of Groningen, The Netherlands
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2020 – today
- 2024
[j4]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits 59(4): 1235-1245 (2024)- 2023
- [c10]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j3]Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang:
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. IEEE J. Solid State Circuits 57(11): 3490-3502 (2022) - [c9]Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang:
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. VLSI Technology and Circuits 2022: 208-209 - [c8]Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn:
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits 2022: 264-265 - 2021
- [j2]Wei Tang, Chia-Hsiang Chen, Zhengya Zhang:
A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System. IEEE J. Solid State Circuits 56(6): 1722-1731 (2021) - [c7]Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang:
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits 2021: 1-2 - [c6]Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang:
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [j1]Wei Tang, Chia-Hsiang Chen, Zhengya Zhang:
A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS. IEEE J. Solid State Circuits 54(7): 2070-2080 (2019) - [c5]Teyuh Chou, Wei Tang, Jacob Botimer, Zhengya Zhang:
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. MICRO 2019: 114-125 - 2018
- [c4]Shiming Song, Wei Tang, Thomas Chen, Zhengya Zhang:
LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS. CICC 2018: 1-4 - [c3]Wei Tang, Hemanth Prabhu, Liang Liu, Viktor Öwall, Zhengya Zhang:
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. ISSCC 2018: 224-226 - 2016
- [c2]Wei Tang, Chia-Hsiang Chen, Zhengya Zhang:
A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector. VLSI Circuits 2016: 1-2 - 2015
- [c1]Chia-Hsiang Chen, Wei Tang, Zhengya Zhang:
18.7 A 2.4mm2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS. ISSCC 2015: 1-3
Coauthor Index
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