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ORCIDShrirang K. Karandikar
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2010 – 2019
- 2012
[c8]Varad R. Deshmukh, Nishchay S. Mhatre, Shrirang K. Karandikar:
FIRA - a novel method for benchmarking the cache hierarchy. COMPUTE 2012: 14
2000 – 2009
- 2008
- [j5]Shrirang K. Karandikar, Sachin S. Sapatnekar
:
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 45-58 (2008) - 2007
- [j4]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [j3]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2009-2022 (2007) - [c7]Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud:
Fast Electrical Correction Using Resizing and Buffering. ASP-DAC 2007: 553-558 - [c6]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - 2006
- [c5]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 - 2005
- [j2]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast comparisons of circuit implementations. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1329-1339 (2005) - [c4]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) 2005: 3575-3578 - 2004
- [c3]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast Comparisons of Circuit Implementations. DATE 2004: 910-915 - [c2]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Logical effort based technology mapping. ICCAD 2004: 419-422 - 2003
- [j1]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1094-1105 (2003) - 2001
- [c1]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. DAC 2001: 377-382
Coauthor Index
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