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ORCIDJayesh Gaur
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Journal Articles
- 2017
[j1]Mainak Chaudhuri, Mukesh Agrawal, Jayesh Gaur, Sreenivas Subramoney
:
Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches. ACM Trans. Archit. Code Optim. 14(1): 7:1-7:29 (2017)
Conference and Workshop Papers
- 2024
- [c17]Rahul Bera, Adithya Ranganathan, Joydeep Rakshit, Sujit Mahto, Anant V. Nori, Jayesh Gaur, Ataberk Olgun, Konstantinos Kanellopoulos, Mohammad Sadrosadati, Sreenivas Subramoney, Onur Mutlu:
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution. ISCA 2024: 88-102 - 2022
- [c16]Sudhanshu Shukla, Sumeet Bandishte, Jayesh Gaur, Sreenivas Subramoney:
Register file prefetching. ISCA 2022: 410-423 - [c15]Logan Moody, Wei Qi, Abdolrasoul Sharifi, Layne Berry, Joey Rudek, Jayesh Gaur, Jeff Parkhurst, Sreenivas Subramoney, Kevin Skadron, Ashish Venkat:
Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations. MICRO 2022: 162-180 - 2021
- [c14]Zhengrong Wang, Jian Weng, Jason Lowe-Power, Jayesh Gaur, Tony Nowatzki:
Stream Floating: Enabling Proactive and Decentralized Cache Optimizations. HPCA 2021: 640-653 - [c13]Michael LeMay, Joydeep Rakshit, Sergej Deutsch, David M. Durham, Santosh Ghosh, Anant Nori, Jayesh Gaur, Andrew Weiler, Salmin Sultana, Karanvir Grewal, Sreenivas Subramoney:
Cryptographic Capability Computing. MICRO 2021: 253-267 - 2020
- [c12]Sumeet Bandishte, Jayesh Gaur, Zeev Sperber, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney:
Focused Value Prediction. ISCA 2020: 79-91 - [c11]Adarsh Chauhan, Jayesh Gaur, Zeev Sperber, Franck Sala, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney:
Auto-Predication of Critical Branches. ISCA 2020: 92-104 - 2019
- [c10]Mainak Chaudhuri, Jayesh Gaur, Sreenivas Subramoney:
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth. ICCD 2019: 109-118 - [c9]Stephen J. Tarsa, Rangeen Basu Roy Chowdhury, Julien Sebot, Gautham N. Chinya, Jayesh Gaur, Karthik Sankaranarayanan, Chit-Kwan Lin, Robert Chappell, Ronak Singhal, Hong Wang:
Post-silicon CPU adaptation made practical using machine learning. ISCA 2019: 14-26 - 2018
- [c8]Anant Nori, Jayesh Gaur, Siddharth Rai, Sreenivas Subramoney, Hong Wang:
Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies. ISCA 2018: 96-109 - [c7]Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang:
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. ISCA 2018: 315-327 - 2017
- [c6]Jayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney:
Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources. HPCA 2017: 13-24 - 2016
- [c5]Jayesh Gaur, Alaa R. Alameldeen, Sreenivas Subramoney:
Base-Victim Compression: An Opportunistic Cache Compression Architecture. ISCA 2016: 317-328 - 2013
- [c4]Jayesh Gaur, Raghuram Srinivasan, Sreenivas Subramoney, Mainak Chaudhuri:
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads. MICRO 2013: 395-407 - 2012
- [c3]Mainak Chaudhuri, Jayesh Gaur, Nithiyanandan Bashyam, Sreenivas Subramoney, Joseph Nuzman:
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches. PACT 2012: 293-304 - 2011
- [c2]Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney:
Bypass and insertion algorithms for exclusive last-level caches. ISCA 2011: 81-92 - 2007
- [c1]Lovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange:
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation. DAC 2007: 69-74
Informal and Other Publications
- 2024
- [i2]Rahul Bera, Adithya Ranganathan, Joydeep Rakshit, Sujit Mahto, Anant V. Nori, Jayesh Gaur, Ataberk Olgun, Konstantinos Kanellopoulos, Mohammad Sadrosadati, Sreenivas Subramoney, Onur Mutlu:
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution. CoRR abs/2406.18786 (2024) - 2018
- [i1]Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang:
MARS: Memory Aware Reordered Source. CoRR abs/1808.03518 (2018)
Coauthor Index
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