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ORCIDFredrik Dahlgren
Person information
- affiliation: Chalmers University of Technology, Gothenburg, Sweden
- affiliation: Uppsala University, Sweden
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Journal Articles
- 2007
[j13]Fredrik Dahlgren:
Partial Continuous Functions and Admissible Domain Representations. J. Log. Comput. 17(6): 1063-1081 (2007)- 2004
- [j12]Fredrik Dahlgren:
Computability and continuity in metric partial algebras equipped with computability structures. Math. Log. Q. 50(4-5): 486-500 (2004) - 1999
- [j11]Fredrik Dahlgren, Josep Torrellas:
Cache-Only Memory Architectures. Computer 32(6): 72-79 (1999) - [j10]Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström:
Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. 56(2): 122-143 (1999) - [j9]Fredrik Dahlgren:
Techniques for Improving Performance of Hybrid Snooping Cache Protocols. J. Parallel Distributed Comput. 59(3): 329-359 (1999) - 1998
- [j8]Fredrik Dahlgren, Jonas Skeppstedt, Per Stenström:
An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols. Future Gener. Comput. Syst. 13(6): 469-487 (1998) - [j7]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. IEEE Trans. Computers 47(10): 1041-1055 (1998) - 1997
- [j6]Fredrik Dahlgren, Per Stenström, Mårten Björkman:
Reducing the Read-Miss Penalty for Flat COMA Protocols. Comput. J. 40(4): 208-219 (1997) - [j5]Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn
, Michel Dubois:
Boosting the Performance of Shared Memory Multiprocessors. Computer 30(7): 63-70 (1997) - 1996
- [j4]Per Stenström, Fredrik Dahlgren:
Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). Computer 29(12): 29-31 (1996) - [j3]Fredrik Dahlgren, Per Stenström:
Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 7(4): 385-398 (1996) - 1995
- [j2]Fredrik Dahlgren, Per Stenström:
Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. 26(2): 193-210 (1995) - [j1]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 6(7): 733-746 (1995)
Conference and Workshop Papers
- 2015
- [c26]Angelos Arelakis, Fredrik Dahlgren, Per Stenström:
HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. MICRO 2015: 38-49 - 2006
- [c25]Fredrik Dahlgren:
Partial Continuous Functions and Admissible Domain Representations. CiE 2006: 94-104 - 2002
- [c24]Magnus Ekman, Per Stenström, Fredrik Dahlgren:
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ISLPED 2002: 243-246 - 2001
- [c23]Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec:
Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par 2001: 385 - [c22]Fredrik Dahlgren:
Future Mobile Phones - Complex Design Challenges from an Embedded Systems Perspective. ICECCS 2001: 92- - 2000
- [c21]Magnus Karlsson, Fredrik Dahlgren, Per Stenström:
A Prefetching Technique for Irregular Accesses to Linked Data Structures. HPCA 2000: 206-217 - [c20]Martin Kämpe, Fredrik Dahlgren:
Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. IPDPS 2000: 163-170 - [c19]Jim Nilsson, Fredrik Dahlgren:
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors. IPDPS 2000: 684-692 - [c18]Ashley Saulsbury, Fredrik Dahlgren, Per Stenström:
Recency-based TLB preloading. ISCA 2000: 117-127 - 1999
- [c17]Jim Nilsson, Fredrik Dahlgren:
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. ICPP 1999: 246-257 - [c16]Ashley Saulsbury, Su-Jaen Huang, Fredrik Dahlgren:
Efficient management of memory hierarchies in embedded DRAM systems. International Conference on Supercomputing 1999: 464-473 - 1998
- [c15]Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal:
The Sensitivity of Communication Mechanisms to Bandwidth and Latency. HPCA 1998: 37-46 - [c14]Peter S. Magnusson, Fredrik Larsson, Andreas Moestedt, Bengt Werner, Jim Nilsson, Per Stenström, Fredrik Lundholm, Magnus Karlsson, Fredrik Dahlgren, Håkan Grahn:
SimICS/Sun4m: A Virtual Workstation. USENIX ATC 1998 - [c13]Per Stenström, Fredrik Dahlgren:
A holistic approach to computer system design education based on system simulation techniques. WCAE@ISCA 1998: 13 - 1997
- [c12]Fredrik Dahlgren, Anders Landin:
Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors. HPCA 1997: 14-23 - 1996
- [c11]Anders Landin, Fredrik Dahlgren:
Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. HPCA 1996: 95-105 - 1995
- [c10]Mårten Björkman, Fredrik Dahlgren, Per Stenström:
Using hints to reduce the read miss penalty for flat COMA protocols. HICSS (1) 1995: 242-251 - [c9]Fredrik Dahlgren, Per Stenström:
Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. HPCA 1995: 68-77 - [c8]Fredrik Dahlgren:
Boosting the Performance of Hybrid Snooping Cache Protocols. ISCA 1995: 60-69 - 1994
- [c7]Fredrik Dahlgren, Per Stenström:
Reducing the Write Traffic for a Hybrid Cache Protocol. ICPP (1) 1994: 166-173 - [c6]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Combined Performance Gains of Simple Cache Protocol Extensions. ISCA 1994: 187-197 - 1993
- [c5]Mats Brorsson, Fredrik Dahlgren, Håkan Nilsson, Per Stenström:
The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors. Annual Simulation Symposium 1993: 41-49 - [c4]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. ICPP (1) 1993: 56-63 - 1991
- [c3]Fredrik Dahlgren:
A program-driven simulation model of an MIMD multiprocessor. Annual Simulation Symposium 1991: 40-49 - [c2]Per Stenström, Fredrik Dahlgren, Lars Lundberg:
A Lockup-Free Multiprocessor Cache Design. ICPP (1) 1991: 246-250 - [c1]Fredrik Dahlgren, Per Stenström:
On Reconfigurable On-Chip Data Caches. MICRO 1991: 189-198
Coauthor Index
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