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ORCIDYuuki Araga
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2020 – today
- 2021
[j6]Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata
, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18(9): 20210070 (2021)- [j5]Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express 18(11): 20210139 (2021) - 2020
- [j4]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55(10): 2747-2755 (2020)
2010 – 2019
- 2019
- [c9]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. 3DIC 2019: 1-3 - [c8]Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC 2019: 1-4 - [c7]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC 2019: 25-28 - 2018
- [j3]Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne:
A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express 15(13): 20180460 (2018) - 2015
- [c6]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Guard-ring monitoring system for inspecting defects in TSV-based data buses. 3DIC 2015: TS8.18.1-TS8.18.5 - 2014
- [c5]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Substrate monitoring system for inspecting defects in TSV-based data buses. 3DIC 2014: 1-5 - 2013
- [j2]Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata:
Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2516-2523 (2013) - [c4]Akitaka Murata, Shuji Agatsuma, Daisaku Ikoma, Kouji Ichikawa, Takahiro Tsuda, Makoto Nagata, Kumpei Yoshikawa, Yuuki Araga, Yuji Harada:
Noise analysis using on-chip waveform monitor in bandgap voltage references. EMC Compo 2013: 226-231 - 2011
- [j1]Takushi Hashida, Yuuki Araga, Makoto Nagata:
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. IEICE Trans. Electron. 94-C(6): 1016-1023 (2011) - [c3]Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne:
In-tier diagnosis of power domains in 3D TSV ICs. 3DIC 2011: 1-6 - [c2]Takushi Hashida, Yuuki Araga, Makoto Nagata:
A diagnosis testbench of analog IP cores against on-chip environmental disturbances. VTS 2011: 70-75 - 2010
- [c1]Yuuki Araga, Takushi Hashida, Makoto Nagata:
An on-chip waveform capturing technique pursuing minimum cost of integration. ISCAS 2010: 3557-3560
Coauthor Index
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