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ORCID3DIC 2015: Sendai, Japan
- 2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015. IEEE 2015, ISBN 978-1-4673-9385-0
- Eric Beyne:
3D system integration research at IMEC. FS1.1 - K. W. Lee, Ji Chel Bea, Mitsu Koyanagi, Takafumi Fukushima
, Tetsu Tanaka:
Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University. FS2.1-FS2.5 - Wei-Chung Lo:
3D research activities in ITRI. FS3.1 - Andy Heinig, Muhammad Waqas Chaudhary, Peter Schneider, Peter Ramm, Josef Weber:
Current and future 3D activities at Fraunhofer. FS4.1-FS4.3 - Vempati Srinivasa Rao:
IME's capabilities and programs in 2.5D/3DIC. FS5.1 - Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy:
3D advanced integration technology for heterogeneous systems. FS6.1-FS6.3 - Daniel S. Green, Carl L. Dohrman, Jeffrey Demmin, Tsu-Hsi Chang:
Path to 3D heterogeneous integration. FS7.1-FS7.3 - Subramanian S. Iyer:
Invited talk: Some challenges in scaling 3D ICs to a broader application set. TS1.1.1 - K. W. Lee, Chisato Nagai, Ai Nakamura, Hiroki Aizawa, Ji Chel Bea, Mitsumasa Koyanagi, Hideto Hashiguchi, Takafumi Fukushima, Tanaka Tanaka:
Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers. TS1.2.1-TS1.2.4 - Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Deprat, Alexandre Ayres De Sousa, Perrine Batude, Claire Fenouillet-Béranger, Fabien Clermidy:
Intermediate BEOL process influence on power and performance for 3DVLSI. TS1.3.1-TS1.3.5 - Amadine Jouve, Y. Sinquin, Arnaud Garnier, M. Daval, Pascal Chausse, M. Argoud, N. Allouti, Laurence Baud, Jérôme Dechamp, R. Franiatte, Séverine Cheramy, H. Kato, K. Kondo:
Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement. TS1.4.1-TS1.4.8 - Robert Patti:
Invited talk: Progress in 3D integrated circuits. TS2.1.1 - Hyunsuk Lee, Kyungjun Cho, Heegon Kim, Sumin Choi, Jaemin Lim, Joungho Kim:
Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module. TS2.2.1-TS2.2.4 - Shuuichi Kariyazaki, Kenichi Kuboyama, Ryuichi Oikawa, Takuo Funaya:
New signal skew cancellation method for 2 Gbps transmission in glass and organic interposers to achieve 2.5D package employing next generation high bandwidth memory (HBM). TS2.3.1-TS2.3.5 - Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka:
Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors. TS3.1.1-TS3.1.4 - Tomoji Nakamura, Yoriko Mizushima, Young-Suk Kim, Ryuichi Sugie, Takayuki Ohba:
Characterization of stress distribution in ultra-thinned DRAM wafer. TS3.2.1-TS3.2.5 - Kazuo Kondo, Shingo Mukahara, Masayuki Yokoi, Jin Onuki:
No pumping at 450°C with electrodeposited copper TSV. TS4.1.1-TS4.1.4 - Pornvitoo Rittinon, Ken Suzuki, Hideo Miura:
Thermal stability of electroplated copper thin-film interconnections. TS4.2.1-TS4.2.6 - Tomoharu Ogita:
Invited talk: Technology and overview of Sony's 3D stacked CMOS image sensor. TS9.1.1 - Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers. TS9.2.1-TS9.2.4 - Mostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz:
Fine-grained 3-D integrated circuit fabric using vertical nanowires. TS9.3.1-TS9.3.7 - Xin Wu:
3D-IC technologies and 3D FPGA. KN1.1-KN1.4 - Tadashi Kamada:
The issues of automated driving vehicle and the expectations for 3D integration technology. KN2.1-KN2.4 - Chung H. Lam:
Neuromorphic semiconductor memory. KN3.1-KN3.4 - Rozalia Beica:
3D integration: Applications and market trends. TS5.1.1-TS5.1.7 - Yangyang Yan, Yingtao Ding, Qianwen Chen, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi:
Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. TS5.2.1-TS5.2.5 - Hiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata:
Nano-Function materials for TSV technologies. TS5.3.1-TS5.3.6 - Ryo Takigawa, Kohei Nitta, Akihiro Ikeda, Mitsuaki Kumazawa, Toshiharu Hirai, Michio Komatsu, Tanemasa Asano:
High-speed via hole filling using electrophoresis of Ag nanoparticles. TS5.4.1-TS5.4.4 - Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa:
Computing in 3D. TS6.1.1-TS6.1.2 - Shogo Hachiya, Takahiro Onagi, Sheyang Ning, Ken Takeuchi:
Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory. TS6.2.1-TS6.2.5 - Chuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Chang, En-Hsiang Yeh, Feng-Wei Kuo, Hsu-Hsien Chen, Chih-Hua Chen, Huan-Neng Ron Chen, Ying-Ta Lu, Chewnpu Jou, Hao-Yi Tsai, C. S. Liu, Doug C. H. Yu:
Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology. TS6.3.1-TS6.3.4 - Gaël Pillonnet, Nicolas Jeanniot, Pascal Vivet:
3D ICs: An opportunity for fully-integrated, dense and efficient power supplies. TS6.4.1-TS6.4.8 - Isao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, Kazuya Okamoto:
New precision wafer bonding technologies for 3DIC. TS7.1.1-TS7.1.7 - Soon-Wook Kim, Lan Peng, Andy Miller, Gerald Beyer, Eric Beyne, Chung-Sun Lee:
Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics. TS7.2.1-TS7.2.4 - Noboru Asahi, Yoshinori Miyamoto, Masatsugu Nimura, Yoshihito Mizutani, Yoshiyuki Arai:
High productivity thermal compression bonding for 3D-IC. TS7.3.1-TS7.3.5 - Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi:
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. TS7.4.1-TS7.4.4 - Kosuke Yamashita, Shunji Kurooka, Koji Shirakawa, Yoshinori Hotta, Hirofumi Abe:
Copper-filled anodized aluminum oxide a potential material for chip to chip bonding. TS8.1.1-TS8.1.5 - Hiroshi Taka, Katsumasa Suzuki, Norihiro Tsujioka, Shoichi Murakami:
Development of high-quality low-temperature (≤ 120°C) PECVD-SiN films by organosilane. TS8.2.1-TS8.2.4 - Kuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii:
Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration. TS8.3.1-TS8.3.5 - Kohei Ohta, Atsushi Hirate, Yuto Miyachi, Tomohiro Shimizu, Shoso Shingubara:
All-wet TSV filling with highly adhesive displacement plated Cu seed layer. TS8.4.1-TS8.4.3 - Jiatong Liu, Ken Suzuki, Hideo Miura:
Variation of thermal stress in TSV structures caused by crystallinity of electroplated copper interconnections. TS8.5.1-TS8.5.5 - Tung Thanh Bui, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi:
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. TS8.6.1-TS8.6.4 - Cui Huang, Dong Wu, Liyang Pan, Zheyao Wang:
Air-gap/SiO2 liner TSVs with improved electrical performance. TS8.7.1-TS8.7.5 - Tsung-Yen Tsai, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen:
An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration. TS8.8.1-TS8.8.5 - Yuan Yuan Dai, Mei Zhen Ng, P. Anantha, Chee Lip Gan, Chuan Seng Tan:
Copper micro and nano particles mixture for 3D interconnections application. TS8.9.1-TS8.9.5 - Mariappan Murugesan, Jichoel Bea, Hiroyuki Hashimoto, K. W. Lee, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study. TS8.10.1-TS8.10.5 - Takahide Murayama, Yasuhiro Morikawa:
TSV etching and VDP process integration for high reliability. TS8.11.1-TS8.11.4 - Chuan-An Cheng, Ryuichi Sugie, Tomoyuki Uchida, Kou-Hua Chen, Chi-Tsung Chiu, Kuan-Neng Chen:
Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration. TS8.12.1-TS8.12.4 - Asisa Kumar Panigrahi, Satish Bonam, Tamal Ghosh, Siva Rama Krishna Vanjari, Shiv Govind Singh:
Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bonding. TS8.13.1-TS8.13.5 - Jin Kawakita, Barbara Horváth, Toyohiro Chikyow:
Fast filling of through-silicon via (TSV) with conductive polymer/metal composites. TS8.14.1-TS8.14.5 - Keiichiro Iwanabe, Tanemasa Asano:
Room-temperature bonding mechanism of compliant bump with ultrasonic assist. TS8.15.1-TS8.15.4 - Ryouya Shirahama, Sethavut Duangchan, Yusuke Koishikawa, Akiyoshi Baba:
Influential factors in low-temperature direct bonding of silicon dioxide. TS8.16.1-TS8.16.5 - Sayuri Kohara, Keishi Okamoto, Hirokazu Noma, Kazushige Toriyama, Hiroyuki Mori:
Warpage analysis of organic substrates for 2.1D packaging. TS8.17.1-TS8.17.5 - Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Guard-ring monitoring system for inspecting defects in TSV-based data buses. TS8.18.1-TS8.18.5 - Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Electrical interconnect test method of 3D ICs by injected charge volume. TS8.19.1-TS8.19.6 - Chao Song, Minxuan Zhang:
Improved access pattern for ROB soft error rate mitigation based on 3D integration technology. TS8.20.1-TS8.20.5 - Arun Raghupathy, Hoa Do, Brian Philofsky, Gamal Refai-Ahmed:
Best engineering practice for thermal characterization of stacked dice FPGA devices. TS8.21.1-TS8.21.8 - Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. TS8.22.1-TS8.22.5 - Gopi Neela, Jeffrey Draper:
Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC. TS8.23.1-TS8.23.6 - Hiroyuki Yotsuyanagi, Akihiro Fujiwara, Masaki Hashizume:
On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs. TS8.24.1-TS8.24.4 - Sumin Choi, Heegon Kim, Daniel H. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yong-Ju Kim, Yunsaing Kim:
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC. TS8.25.1-TS8.25.5 - Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka:
Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC. TS8.26.1-TS8.26.4 - Eric J. Wyers, T. Robert Harris, Wallace Shep Pitts, Jordan E. Massad, Paul D. Franzon:
Characterization of the mechanical stress impact on device electrical performance in the CMOS and III-V HEMT/HBT heterogeneous integration environment. TS8.27.1-TS8.27.4 - Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi:
Design of a 3-D stacked floating-point Goldschmidt divider. TS8.28.1-TS8.28.4 - Daniel H. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi:
Modeling and analysis of defects in through silicon via channel for non-invasive fault isolation. TS8.29.1-TS8.29.4 - Samson Melamed, Katsuya Kikuchi, Masahiro Aoyagi:
Investigation of effects of metalization on heat spreading in bump-bonded 3D systems. TS8.30.1-TS8.30.4 - Andy Heinig, Robert Fischbach:
Enabling automatic system design optimization through Assembly Design Kits. TS8.31.1-TS8.31.5 - Armin Grünewald, Michael G. Wahl, Rainer Brück:
Cost modeling and analysis for the design, manufacturing and test of 3D-ICs. TS8.32.1-TS8.32.6 - Mohamed N. ElBahey, DiaaEldin S. Khalil, Hani Fikry Ragai:
Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA). TS8.33.1-TS8.33.4 - Insu Hwang, Jihye Kim, Youngwoo Kim, Jonghyun Cho, Joungho Kim:
Noise coupling modeling and analysis of through glass via(TGV). TS8.34.1-TS8.34.5 - R. Ranga Reddy, Sugandh Tanna, Shiv Govind Singh, Om Krishna Singh:
TSV noise coupling in 3D IC using guard ring. TS8.35.1-TS8.35.5 - Susheela Narasimhan:
Power tile optimization and packaging for efficient temperature management of ASIC's in networking applications. TS8.36.1 - Gamal Refai-Ahmed, Ivor Barber, Anthony Torza, Brian Philofsky:
A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applications. TS10.1.1-TS10.1.4 - T. Robert Harris, Eric J. Wyers, Lee Wang, Samuel Graham, Georges Pavlidis, Paul D. Franzon, W. Rhett Davis:
Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks. TS10.2.1-TS10.2.4 - Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Temperature-aware online testing of power-delivery TSVs. TS10.3.1-TS10.3.6 - Cristiano Santos, Rafael Prieto, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Reis:
Graphite-based heat spreaders for hotspot mitigation in 3D ICs. TS10.4.1-TS10.4.4 - Joungho Kim:
Active Si interposer for 3D IC integrations. TS11.1.1-TS11.1.3 - Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne:
Processing active devices on Si interposer and impact on cost. TS11.2.1-TS11.2.4 - Hanju Oh, Gary S. May, Muhannad S. Bakir:
Silicon interposer platform with low-loss through-silicon vias using air. TS11.3.1-TS11.3.4 - Benjamin Vianne, Alexis Farcy, Vincent Fiori, Cédrick Chappaz, Norbert Chevrier, G. Lobascio, Pascal Chausse, F. Ponthenier, A. Ruckly, Stéphanie Escoubas, Olivier Thomas:
Stress management strategy to limit die curvature during silicon interposer integration. TS11.4.1-TS11.4.7
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