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Albrecht P. Stroele
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2000 – 2009
- 2001
- [c23]Tobias Schüle, Albrecht P. Stroele:
Scheduling tests for low power built-in self-test. ISCAS (5) 2001: 247-250 - [c22]Tobias Schüle, Albrecht P. Stroele:
Test Scheduling for Minimal Energy Consumption under Power Constraints. VTS 2001: 312-318 - 2000
- [j5]Albrecht P. Stroele, Steffen Tarnick:
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes. J. Electron. Test. 16(4): 355-367 (2000) - [c21]Albrecht P. Stroele:
Synthesizing data paths with arithmetic self-test. ISCAS 2000: 45-48 - [c20]Frank Mayer, Albrecht P. Stroele:
A Versatile BIST Technique Combining Test Registers and Accumulators. VLSI Design 2000: 412- - [c19]Albrecht P. Stroele:
Synthesis for Arithmetic Built-In Self-Tes. VTS 2000: 165-170
1990 – 1999
- 1999
- [j4]Albrecht P. Stroele:
Signature Analysis for Test Responses of Sequential Circuits. VLSI Design 10(2): 127-141 (1999) - [c18]Albrecht P. Stroele, Frank Mayer:
Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators. Asian Test Symposium 1999: 101-106 - [c17]Albrecht P. Stroele, Steffen Tarnick:
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code. VTS 1999: 361-369 - 1998
- [b2]Albrecht P. Ströle:
Entwurf selbsttestbarer Schaltungen. Teubner-Texte zur Informatik 27, Teubner 1998, ISBN 978-3-8154-2314-1, pp. 1-322 - [j3]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Hardware-optimal test register insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 531-539 (1998) - [j2]Gerald Spiegel, Albrecht P. Stroele:
Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults. VLSI Design 7(2): 163-176 (1998) - [c16]Frank Mayer, Albrecht P. Stroele:
Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit. Asian Test Symposium 1998: 15-20 - [c15]Steffen Tarnick, Albrecht P. Stroele:
Embedded self-testing checkers for low-cost arithmetic codes. ITC 1998: 514-523 - [c14]Albrecht P. Stroele:
Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions. VTS 1998: 78-85 - 1997
- [j1]Albrecht P. Stroele:
BIST Pattern Generators Using Addition and Subtraction Operations. J. Electron. Test. 11(1): 69-80 (1997) - [c13]Albrecht P. Stroele, Frank Mayer:
Methods to reduce test application time for accumulator-based self-test. VTS 1997: 48-53 - 1996
- [c12]Albrecht P. Stroele:
Arithmetic Pattern Generators for Built-In Self-Test. ICCD 1996: 131-134 - [c11]Albrecht P. Stroele:
Test response compaction using arithmetic functions. VTS 1996: 380-386 - 1995
- [c10]Gerald Spiegel, Albrecht P. Stroele:
A unified approach to the extraction of realistic multiple bridging and break faults. EURO-DAC 1995: 184-189 - [c9]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Test register insertion with minimum hardware cost. ICCAD 1995: 95-101 - [c8]Albrecht P. Stroele:
A Self-Test Approach Using Accumulators as Test Pattern Generators. ISCAS 1995: 2120-2123 - [c7]Albrecht P. Stroele:
Signature analysis and aliasing for sequential circuits. VTS 1995: 118-124 - 1994
- [c6]Albrecht P. Stroele:
Signature Analysis for Sequential Circuits with Reset. EDAC-ETC-EUROASIC 1994: 113-118 - [c5]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Configuring Flip-Flops to BIST Registers. ITC 1994: 939-948 - 1993
- [c4]Albrecht P. Stroele:
Partitioning and hierarchical description of self-testable designs. VLSI 1993: 113-122 - 1992
- [b1]Albrecht P. Ströle:
Testablaufplanung und Testauswertung für selbsttestbare Schaltungen. Karlsruhe Institute of Technology, Germany, VDI-Verlag 1992, ISBN 978-3-18-142010-2, pp. 1-118 - [c3]Albrecht P. Stroele:
Self-Test Scheduling with Bounded Test Execution. ITC 1992: 130-139 - 1991
- [c2]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Signature Analysis and Test Scheduling for Self-Testable Circuits. FTCS 1991: 96-103 - 1990
- [c1]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Error masking in self-testable circuits. ITC 1990: 544-552
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