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ORCIDVTS 1995: Princeton, NJ, USA
- 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA. IEEE Computer Society 1995, ISBN 0-8186-7000-2
Advanced Test Pattern Generation Methods
- David E. Long, Mahesh A. Iyer, Miron Abramovici:
Identifying sequentially untestable faults using illegal states. 4-11 - Srimat T. Chakradhar, Steven G. Rothweiler:
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. 12-19 - Mark C. Hansen, John P. Hayes:
High-level test generation using physically-induced faults. 20-28 - Fulvio Corno
, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva:
A portable ATPG tool for parallel and distributed systems. 29-34 - Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis:
Testing combinational iterative logic arrays for realistic faults. 35-41
Mixed-Signal Circuit Test
- Ashok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham:
Verification of transient response of linear analog circuits. 42-47 - Diego Vázquez, Adoración Rueda, José L. Huertas:
A solution for the on-line test of analog ladder filters. 48-53 - Khaled Saab, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski:
Frequency-based BIST for analog circuit testin. 54-59 - Stephen K. Sunter:
A low cost 100 MHz analog test bus. 60-65 - Lahouari Sebaa, Norm Gardner, Robert Neidorff, Rich Valley:
Self-test in a VCM driver chip. 66-73
Defect Coverage and Test Quality
- Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams:
On the decline of testing efficiency as fault coverage approaches 100%. 74-83 - Peter C. Maxwell:
The use of IDDQ testing in low stuck-at coverage situations. 84-88 - Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel:
Cyclic stress tests for full scan circuits. 89-94 - Jaume A. Segura, Miquel Roca, Diego Mateo, Antonio Rubio:
An approach to dynamic power consumption current testing of CMOS ICs. 95-100 - Javier Argüelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho:
Iddt testing of continuous-time filters. 101-107
Advanced BIST Approaches
- Jacob Savir:
On shrinking wide compressors. 108-117 - Albrecht P. Stroele:
Signature analysis and aliasing for sequential circuits. 118-124 - Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao:
An apparatus for pseudo-deterministic testing. 125-131 - Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer:
Arithmetic built-in self test for high-level synthesis. 132-139 - Jeffrey A. Floyd, Matt Perry:
Real-time on-board bus testing. 140-151
Synthesis for Testability
- Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Resynthesis for sequential circuits designed with a specified initial state. 152-157 - Frank F. Hsu, Janak H. Patel:
A distance reduction approach to design for testability. 158-163 - Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja:
An optimized testable architecture for finite state machines. 164-169 - Mahsa Vahidi, Alex Orailoglu:
Testability metrics for synthesis of self-testable designs and effective test plans. 170-175 - Xinli Gu:
RT level testability-driven partitioning. 176-183
Fault Modeling
- Michel Renovell, P. Huc, Yves Bertrand:
The concept of resistance interval: a new parametric model for realistic resistive bridging fault. 184-189 - Ding Lu, Carol Q. Tong:
High level fault modeling of asynchronous circuits. 190-195 - Samy Makar, Edward J. McCluskey:
Checking experiments to test latches. 196-201 - Víctor H. Champac, Joan Figueras:
Testability of floating gate defects in sequential circuits. 202-207 - Peter Lidén, Peter Dahlgren:
Switch-level modeling of transistor-level stuck-at faults. 208-215
Fault Simulation I
- Tapan J. Chakraborty, Vishwani D. Agrawal:
Simulation of at-speed tests for stuck-at faults. 216-220 - Rajesh Nair, Dong Sam Ha:
VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits. 221-226 - Marc D. Riedel, Janusz Rajski:
Fault coverage analysis of RAM test algorithms. 227-234 - Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò:
Reliability evaluation of combinational logic circuits by symbolic simulation. 235-243
Fault Diagnosis
- Charles E. Stroud, T. Raju Damarla:
Improving the efficiency of error identification via signature analysis. 244-249 - Samantha Edirisooriya, Geetani Edirisooriya:
Diagnosis of scan path failures. 250-255 - Tong Liu, Fabrizio Lombardi, José Salinas:
Diagnosis of interconnects and FPICs using a structured walking-1 approach. 256-261 - Claude Thibeault:
Detection and location of faults and defects using digital signal processing. 262-269
Design for Testability
- Sridhar Narayanan, Melvin A. Breuer:
Asynchronous multiple scan chain. 270-276 - Kwang-Ting Cheng:
Partial scan designs without using a separate scan clock. 277-282 - Ajay Khoche, Erik Brunvand:
A partial scan methodology for testing self-timed circuits. 283-289 - Mohamed Soufi, Yvon Savaria, Bozena Kaminska:
On the design of at-speed testable VLSI circuits. 290-295 - O. A. Petlin, Stephen B. Furber:
Scan testing of micropipelines. 296-303
Iddq Testing
- Marcello Dalpasso, Michele Favalli, Piero Olivo:
Test pattern generation for IDDQ: increasing test quality. 304-309 - Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara:
Compact test generation for bridging faults under IDDQ testing. 310-316 - Udo Mahlstedt, Jürgen Alt, Matthias Heinitz:
CURRENT: a test generation system for IDDQ testing. 317-323 - Josep Rius, Joan Figueras:
Detecting IDDQ defective CMOS circuits by depowering. 324-329 - Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira:
Test preparation for high coverage of physical defects in CMOS digital ICs. 330-337
Automatic Test Pattern Generation
- Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus:
Improving topological ATPG with symbolic techniques. 338-343 - Tomoo Inoue, Hironori Maeda, Hideo Fujiwara:
A scheduling problem in test generation. 344-349 - Andrej Zemva, Franc Brglez:
Detectable perturbations: a paradigm for technology-specific multi-fault test generation. 350-357 - M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Compact test sets for industrial circuits. 358-366 - Bapiraju Vinnakota, Nicholas J. Stessman:
Reducing test application time in scan design schemes. 367-373
Delay Fault Testing
- Angela Krstic, Kwang-Ting Cheng:
Generation of high quality tests for functional sensitizable paths. 374-379 - Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
Diagnostic of path and gate delay faults in non-scan sequential circuits. 380-386 - Harry Hengster, Rolf Drechsler, Bernd Becker:
On the application of local circuit transformations with special emphasis on path delay fault testability. 387-392 - Imtiaz P. Shaik, Michael L. Bushnell:
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . 393-399 - Wuudiann Ke, Premachandran R. Menon:
Multifault testability of delay-testable circuits. 400-409
Test Pattern Generation for BIST
- Nur A. Touba, Edward J. McCluskey:
Transformed pseudo-random patterns for BIST. 410-416 - Mitrajit Chatterjee, Dhiraj K. Pradhan:
A novel pattern generator for near-perfect fault-coverage. 417-425 - Nadime Zacharia, Janusz Rajski, Jerzy Tyszer:
Decompression of test data using variable-length seed LFSRs. 426-433 - Samir Lejmi, Bozena Kaminska, Bechir Ayari:
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits. 434-439 - Günter Kemnitz:
Synthesis of locally exhaustive test pattern generators. 440-447
Self-Checking Systems I
- Samvel K. Shoukourian, Armen G. Kostanian, Valery A. Margarian, Ayman A. Ashour:
An approach for system tests design and its application. 448-453 - Alessandro Bogliolo, Maurizio Damiani:
Synthesis of combinational circuits with special fault-handling capabilitie. 454-459 - B. Hamdi, Hakim Bederr, Michael Nicolaidis:
A tool for automatic generation of self-checking data paths. 460-466 - Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen:
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers. 467-471 - Walter W. Weber, Adit D. Singh:
An experimental evaluation of the differential BICS for IDDQ testing. 472-485
Best Paper - 1994
- Joan Carletta, Christos A. Papachristou:
Structural constraints for circular self-test paths. 486-491
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