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David Walter
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2020 – today
- 2023
- [j7]Marco Di Maria
, David Walter
, Thorsten Schoormann
, Ralf Knackstedt:
Design-Challenges im virtuellen Raum - Ein Erfahrungsbericht und Handlungsempfehlungen. HMD Prax. Wirtsch. 60(3): 738-753 (2023) - [c20]Marco Di Maria, David Walter, Paul-Ferdinand Steuck, Ralf Knackstedt:
Mitigating Educational Challenges Through Unlearning. DELFI 2023: 38 - [c19]Marco Di Maria, David Walter, Fabian Segieth, Ralf Knackstedt:
COREFLECTOR - Prototyp zur Unterstützung von Verlernen beim analytischen Lesen für Studierende. DELFI 2023: 42 - [c18]David Walter, Marco Di Maria, Ralf Knackstedt:
Tool-Support for Managing Technostress in Hybrid Learning Settings. DELFI 2023: 63 - [c17]Marco Di Maria, David Walter, Thorsten Schoormann, Ralf Knackstedt:
Practical Support for Unlearning â€" a Systematic Review to Organize the field. ECIS 2023 - [c16]Marco Di Maria, David Walter, Ralf Knackstedt:
Promoting Sustainable Ecosystems through Interorganizational Unlearning - A Call for Research. GI-Jahrestagung 2023: 1351-1358 - [c15]Marco Di Maria, David Walter, Thorsten Schoormann, Ralf Knackstedt:
Designing Unlearning Support Systems: A Requirements Catalog. Wirtschaftsinformatik 2023: 49 - 2022
- [c14]Marco Di Maria, David Walter, Ralf Knackstedt:
THESIS DESIGNER - Eine Webanwendung zur Unterstützung von Abschlussarbeiten. DELFI 2022: 243-244 - [i1]Ayon Basumallik, Darius Bunandar, Nicholas Dronen, Nicholas C. Harris, Ludmila Levkova, Calvin McCarter, Lakshmi Nair, David Walter, David Widemann:
Adaptive Block Floating-Point for Analog Deep Learning Hardware. CoRR abs/2205.06287 (2022)
2010 – 2019
- 2018
- [c13]Rohil Verma, Samuel Kim, David Walter:
Syntactical Analysis of the Weaknesses of Sentiment Analyzers. EMNLP 2018: 1122-1127 - 2014
- [c12]Andrew N. Fisher, Satish Batchu, Kevin R. Jones, Dhanashree Kulkarni, Scott Little, David Walter, Chris J. Myers
:
LEMA: A tool for the formal verification of digitally-intensive analog/mixed-signal circuits. MWSCAS 2014: 1017-1020 - 2013
- [c11]Kostadin Damevski, Badreldin Altayeb, Hui Chen, David Walter
:
Teaching cyber-physical systems to computer scientists via modeling and verification. SIGCSE 2013: 567-572 - 2011
- [j6]Scott Little, David Walter
, Chris J. Myers
, Robert A. Thacker, Satish Batchu, Tomohiro Yoneda:
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 617-630 (2011) - 2010
- [j5]Scott Little, David Walter
, Kevin R. Jones, Chris J. Myers
, Alper Sen:
Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. Int. J. Found. Comput. Sci. 21(2): 191-210 (2010)
2000 – 2009
- 2008
- [j4]David Walter
, Scott Little, Chris J. Myers
, Nicholas Seegmiller, Tomohiro Yoneda:
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2223-2235 (2008) - 2007
- [b1]David Walter:
Verification of Analog and Mixed-Signal Circuits Using Symbolic Methods. University of Utah, USA, 2007 - [c10]David Walter
, Scott Little, Nicholas Seegmiller, Chris J. Myers
, Tomohiro Yoneda:
Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323 - [c9]David Walter
, Scott Little, Chris J. Myers:
Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. ATVA 2007: 66-81 - [c8]Scott Little, David Walter
, Kevin R. Jones, Chris J. Myers:
Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. ATVA 2007: 114-128 - 2006
- [j3]Hao Zheng, Chris J. Myers
, David Walter
, Scott Little, Tomohiro Yoneda:
Verification of timed circuits with failure-directed abstractions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 403-412 (2006) - [c7]Scott Little, Nicholas Seegmiller, David Walter
, Chris J. Myers
, Tomohiro Yoneda:
Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282 - 2005
- [c6]Chris J. Myers
, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little:
The Case for Analog Circuit Verification. FAC 2005: 53-63 - 2004
- [c5]Scott Little, David Walter
, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda:
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440 - 2003
- [c4]Hao Zheng, Chris J. Myers, David Walter
, Scott Little, Tomohiro Yoneda:
Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35
1990 – 1999
- 1996
- [c3]David Walter, Jon M. Kerridge:
The Design of the IRISS Parallel Database Machine. HPCN Europe 1996: 913-914 - 1995
- [c2]Jon M. Kerridge
, David Walter, Romola Guiton:
W-SQL: An Interface for Scalable, Highly Parallel Database Machines. BNCOD 1995: 263-276 - 1994
- [j2]David Walter:
Computer art from Newton's, Secant, and Richardson's methods. Comput. Graph. 18(1): 127-131 (1994) - [c1]David Walter, Jon M. Kerridge
:
Large Scale Data Management and Massively Parallel Architectures in Automatic Fingerprint Recognition. HPCN 1994: 435-440 - 1993
- [j1]David Walter:
Systemised serendipity for producing computer art. Comput. Graph. 17(6): 699-700 (1993)
Coauthor Index
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