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Hasitha Muthumala Waidyasooriya
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Journal Articles
- 2024
- [j24]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Performance evaluation of Word2vec accelerators exploiting spatial and temporal parallelism on DDR/HBM-based FPGAs. J. Supercomput. 80(12): 17192-17211 (2024) - 2022
- [j23]Hasitha Muthumala Waidyasooriya
, Hiroki Oshiyama
, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki:
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory. IEEE Access 10: 65103-65117 (2022) - [j22]Mitsuhiro Okada
, Takayuki Suzuki, Naoya Nishio
, Hasitha Muthumala Waidyasooriya
, Masanori Hariyama:
FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services. IEEE Trans. Cloud Comput. 10(2): 1373-1385 (2022) - [j21]Chia-Yin Liu
, Hasitha Muthumala Waidyasooriya
, Masanori Hariyama:
Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. J. Supercomput. 78(1): 1-17 (2022) - [j20]Hasitha Muthumala Waidyasooriya
, Masanori Hariyama:
Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU. J. Supercomput. 78(6): 8733-8750 (2022) - 2021
- [j19]Hasitha Muthumala Waidyasooriya
, Masanori Hariyama:
Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing. IEEE Trans. Emerg. Top. Comput. 9(4): 2019-2029 (2021) - 2020
- [j18]Hasitha Muthumala Waidyasooriya
, Masanori Hariyama:
A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism. IEEE Access 8: 67929-67939 (2020) - 2019
- [j17]Hasitha Muthumala Waidyasooriya
, Masanori Hariyama:
Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability. IEEE Access 7: 53188-53201 (2019) - [j16]Hasitha Muthumala Waidyasooriya
, Masanori Hariyama, Masamichi J. Miyama
, Masayuki Ohzeki
:
OpenCL-based design of an FPGA accelerator for quantum annealing simulation. J. Supercomput. 75(8): 5019-5039 (2019) - 2017
- [j15]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
:
An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL. Int. J. Networked Distributed Comput. 5(1): 52-61 (2017) - [j14]Hasitha Muthumala Waidyasooriya
, Tsukasa Endo
, Masanori Hariyama
, Yasuo Ohtera
:
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. Int. J. Reconfigurable Comput. 2017: 6817674:1-6817674:11 (2017) - [j13]Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama:
OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology. IEEE Trans. Parallel Distributed Syst. 28(5): 1390-1402 (2017) - 2016
- [j12]Hasitha Muthumala Waidyasooriya
, Masanori Hariyama:
Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform. IEEE Trans. Parallel Distributed Syst. 27(5): 1358-1372 (2016) - 2015
- [j11]Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2658-2669 (2015) - 2014
- [j10]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei
, Michitaka Kameyama
:
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. J. Comput. Eng. 2014: 634269:1-634269:8 (2014) - 2013
- [j9]Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2576-2586 (2013) - 2012
- [j8]Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama:
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. 95-D(2): 354-363 (2012) - [j7]Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama:
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. 95-C(12): 1872-1882 (2012) - 2011
- [j6]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 342-351 (2011) - [j5]Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Technol. 21(10): 1453-1466 (2011) - 2010
- [j4]Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama:
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2570-2580 (2010) - 2009
- [j3]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Trans. Electron. 92-C(4): 539-549 (2009) - 2008
- [j2]Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Trans. Electron. 91-C(4): 517-525 (2008) - [j1]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3596-3606 (2008)
Conference and Workshop Papers
- 2022
- [c21]Hasitha Muthumala Waidyasooriya, Yuta Ohma, Masanori Hariyama:
FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model. MCSoC 2022: 195-199 - [c20]Kosiro Obata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++. MWSCAS 2022: 1-4 - [c19]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano:
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS 2022: 1-4 - [c18]Hasitha Muthumala Waidyasooriya, Shutaro Ishihara, Masanori Hariyama:
Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism. PDCAT 2022: 69-77 - 2019
- [c17]Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa:
A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA. CANDAR Workshops 2019: 103-108 - [c16]Chia-Yin Liu
, Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation. CANDAR 2019: 164-170 - [c15]Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama:
Benchmarks for FPGA-Targeted High-Level-Synthesis. CANDAR 2019: 232-238 - [c14]Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa:
FPGA-Based Acceleration of Word2vec using OpenCL. ISCAS 2019: 1-5 - 2018
- [c13]Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama:
Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. ISPACS 2018: 335-340 - [c12]Yuki Hiradate, Hasitha Muthumala Waidyasooriya
, Masanori Hariyama, Masaaki Harada:
Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems. SCFA 2018: 146-155 - 2017
- [c11]Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki:
Architecture of an FPGA accelerator for LDA-based inference. SNPD 2017: 357-362 - 2016
- [c10]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL. ICIS 2016: 1-6 - [c9]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
:
Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL. ICIS 2016: 1-5 - 2015
- [c8]Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama:
Hardware-oriented succinct-data-structure based on block-size-constrained compression. SoCPaR 2015: 136-140 - 2014
- [c7]Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama:
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. APCCAS 2014: 639-642 - 2013
- [c6]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. EMBC 2013: 651-654 - 2012
- [c5]Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama:
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS 2012: 1339-1342 - 2010
- [c4]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA 2010: 179-186 - [c3]Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama:
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA 2010: 281-284 - 2009
- [c2]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA 2009: 291-294 - 2008
- [c1]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA 2008: 201-207
Coauthor Index
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