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Journal Articles
- 2021
[j6]Hayato Yoshida
, Yusaku Shiotsu, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches. IEEE Open J. Circuits Syst. 2: 520-533 (2021)- 2020
- [j5]Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions. IEICE Electron. Express 17(4): 20200032 (2020) - 2010
- [j4]Satoshi Sugahara, Junsaku Nitta:
Spin-Transistor Electronics: An Overview and Outlook. Proc. IEEE 98(12): 2124-2154 (2010) - 2009
- [j3]Kouhei Yamada, Satoshi Sugahara, Nobuo Fujii:
Over Current Protection for PFM Control DC-DC Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(5): 1301-1307 (2009) - 2008
- [j2]Satoshi Sugahara, Kouhei Yamada, Tetsuya Kawashima, Masaharu Edo, Toshiro Sato, Kiyohito Yamasawa:
High Efficiency PWM Controlled Micro DC-DC Converter for Portable Electronic Equipments. IEICE Trans. Commun. 91-B(11): 3704-3711 (2008) - 2006
- [j1]Satoshi Sugahara, Masaaki Tanaka:
Spin MOSFETs as a basis for spintronics. ACM Trans. Storage 2(2): 197-219 (2006)
Conference and Workshop Papers
- 2018
- [c8]Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters. NGCAS 2018: 186-189 - 2016
- [c7]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Energy performance of nonvolatile power-gating SRAM using SOTB technology. ESSCIRC 2016: 95-98 - [c6]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Design and implementation of nonvolatile power-gating SRAM using SOTB technology. ISLPED 2016: 338-343 - 2015
- [c5]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology. DATE 2015: 866-871 - 2014
- [c4]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology. APCCAS 2014: 699-702 - 2013
- [c3]Ryosho Nakane, Yusuke Shuto, Hiroaki Sukegawa, Zhenchao Wen, Shuu'ichirou Yamamoto, Seiji Mitani, Masaaki Tanaka, Koichiro Inomata, Satoshi Sugahara:
Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service. ESSDERC 2013: 272-275 - 2009
- [c2]Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara:
Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices. CICC 2009: 531-534 - 2006
- [c1]Akira Yamazaki, Kouhei Yamada, Satoshi Sugahara:
A Frequency Compensation Technique for Variable Output Low Dropout Regulators. APCCAS 2006: 1595-1598
Coauthor Index
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