Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDCICC 2009: San Jose, California, USA
- IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings. IEEE 2009, ISBN 978-1-4244-4071-9
Session 1 - Keynote Presentation
- Thomas Williams:
Another Inconvenient Truth: Snails Are More Intelligent Than Us.
Session 2 - Over-Sampled Data Converters
- Pavan Kumar Hanumolu, Alessandro Piovaccari:
Over-sampled data converters. - Tawfiq Musah
, Sunwoo Kwon, Hasnain Lakdawala, Krishnamurthy Soumyanath, Un-Ku Moon:
A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS. 1-4 - Mohammad Ranjbar, Arash Mehrabi, Omid Oliaei:
A low-power 1.92MHz CT ΔΣ modulator with 5-bit successive approximation quantizer. 5-8 - Junpei Kamiishi, Yun-Shiang Shu, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator. 9-12 - Minsheng Wang, Xicheng Jiang, Jungwoo Song, Todd Brooks:
A 120dB dynamic range 400mW class-D speaker driver with 4th-order PWM modulator. 13-16
Session 3 - Biomedical Electronics
- Ed Lee:
Biomedical electronics forum.
Session 4 - Nanoscale Power and Performance Optimizations
- Osamu Takahashi, Michael Seningen:
Nanoscale power and performance optimizations. - William Keshlear, Spence Oliver, Robert Colyer, Jeremy Schreiber, Ted Antoniadis, Tom Mickelson, Tim Puzey, Michael Bates:
Design optimizations for reduced power and higher operating frequency in a custom x86-64 processor core. 17-20 - Kenji Shimazaki, Takaaki Okumura:
A minimum decap allocation technique based on simultaneous switching for nanoscale SoC. 21-24 - Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton:
Charge-borrowing decap: A novel circuit for removal of local supply noise violations. 25-28 - Dong Jiao, Jie Gu, Chris H. Kim:
Circuit techniques for enhancing the clock data compensation effect under resonant supply noise. 29-32 - Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test. 33-36
Session 5 - Frequency Synthesizers
- Cicero S. Vaucher, Rick Booth:
Frequency Synthesizers. - Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
Insights into wideband fractional All-Digital PLLs for RF applications. 37-44 - Antonio Liscidini, Luca Vercesi, Rinaldo Castello:
Time to digital converter based on a 2-dimensions Vernier architecture. 45-48 - Mark A. Ferriss, David T. Lin, Michael P. Flynn:
A fractional-N PLL modulator with flexible direct digital phase modulation. 49-52 - Lei Lu, Lingbu Meng, Liang Zou, Hao Min, Zhangwen Tang:
A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique. 53-56 - Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani:
A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology. 57-60 - Enrico Monaco, Mattia Borgarino, Francesco Svelto, Andrea Mazzanti:
A 5.2mW ku-band CMOS injection-locked frequency doubler with differential input / output. 61-64
Session 6 - MEMS, Biomedical, and Sensors
- Hasnain Lakdawala, Kenneth Szajda:
MEMS, biomedicals, and sensors. - Farrokh Ayazi:
MEMS for integrated timing and spectral processing. 65-72 - Amita C. Patil, Xiao-an Fu, Mehran Mehregany, Steven L. Garverick:
Fully-monolithic, 600°C differential amplifiers in 6H-SiC JFET IC technology. 73-76 - Justin A. Richardson, Richard Walker, Lindsay Grant, David Stoppa, Fausto Borghetti, Edoardo Charbon, Marek Gersbach, Robert K. Henderson:
A 32×32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging. 77-80 - Tamal Mukherjee, Gary K. Fedder:
RF-CMOS-MEMS based frequency-reconfigurable amplifiers. 81-84 - Lorenzo Turicchia, Soumyajit Mandal, Maziar Tavakoli, Leon Fay, Vinith Misra, Jose L. Bohorquez, William R. Sanchez, Rahul Sarpeshkar:
Ultra-low-power electronics for non-invasive medical monitoring. 85-92 - Edward K. F. Lee:
High-voltage tolerant stimulation monitoring circuit in conventional CMOS process. 93-96 - Benoit Gosselin, Mohamad Sawan:
Circuits techniques and microsystems assembly for intracortical multichannel ENG recording. 97-104
Session 7 - Gigabit Transceivers and Building Blocks
- Jin Liu, Jim Buckwalter:
Gigabit transceivers and building blocks. - Mike P. Li, Sergey Y. Shumarayev:
Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation. 105-112 - Hao Liu, Jin Liu, Robert Payne, Cy Cantrell, Mark Morgan:
A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS. 113-116 - Dong Hun Shin, Ji-Eun Jang, Frank O'Mahony, C. Patrick Yue:
A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS. 117-120 - Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti:
A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation. 121-124 - Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani:
A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links. 125-128 - Shih-Hao Huang, Wei-Zen Chen:
A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector. 129-132
Session 8 - CMOS Scaling and Beyond
- Takamaro Kikkawa, Jordan Lai:
CMOS scaling and beyond. - Burn J. Lin, R. G. Liu:
Progress and outlook of lithography for semiconductor IC. 133-140 - Jeff Gambino, Fen Chen, John He:
Copper interconnect technology for the 32 nm node and beyond. 141-148 - Manfred Horstmann, Andy Wei, Jan Hoentschel, Thomas Feudel, Thilo Scheiper, Rolf Stephan, Martin Gerhardt, Stephan Krügel, Michael Raab:
Advanced SOI CMOS transistor technologies for high-performance microprocessor applications. 149-152 - Shinichi Takagi:
High mobility channel CMOS technologies for realizing high performance LSI's. 153-160
Poster Session
- Ajay Kumar:
Trimless second order curvature compensated bandgap reference using diffusion resistor. 161-164 - Abhijit Kumar Das, Hemant Bhasin, Sundara Siva Rao Giduturi:
A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply. 165-168 - Lanny L. Lewyn, Markus Loose:
A 1.5mW 16b ADC with improved segmentation and centroiding algorithms and litho-friendly physical design (LFD) used in space telescope imaging applications. 169-170 - Sunwoo Kwon, Pavan Kumar Hanumolu, Sang-Ho Kim, Sung-No Lee, Seung-Bin You, Ho-Jin Park, Jae-Whui Kim, Un-Ku Moon:
An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. 171-174 - Michiko Tokumaru, Heiji Ikoma, Yuji Yamada, Koji Okamoto, Akira Yamamoto, Yoshinori Shirakawa:
A 14.6th-order 3.456GHz transmit baseband filter in 110nm CMOS for millimeter-wave communication systems. 175-178 - Ching Zhou, Bruce M. Fleischer, Michael Gschwind, Ruchir Puri:
64-bit prefix adders: Power-efficient topologies and design solutions. 179-182 - Bita Nezamfar, Mark Horowitz:
Energy-performance tunable logic. 183-186 - Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. 187-190 - Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. 191-194 - Xueqiang Wang, Dong Wu, Chaohong Hu, Liyang Pan, Runde Zhou:
Embedded high-speed BCH decoder for new-generation NOR flash memories. 195-198 - James C. Salvia, Pedram Lajevardi, Mohammad Hekmat, Boris Murmann:
A 56MΩ CMOS TIA for MEMS applications. 199-202 - Kisoo Kim, Hokyu Lee, Sangdon Jung, Chulwoo Kim:
A 366kS/s 400uW 0.0013mm2 frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock. 203-206 - Dick James:
Design-for-manufacturing features in nanometer logic processes - a reverse engineering perspective. 207-210 - Shih-Jung Wang, Yu-Huei Lee, Yung-Chih Lai, Ke-Horng Chen:
Quadratic differential and integration technique in V2 control buck converter with small ESR capacitor. 211-214 - Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. 215-218 - Daisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata:
A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. 219-222 - Xiaozhou Yan, Xiaofei Kuang, Nanjian Wu:
An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction. 223-226 - Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi-Chao Wang, Seung H. Kang, Joseph Wang, Matt Nowak, Nick Yu:
Pathfinding for 22nm CMOS designs using Predictive Technology Models. 227-230 - Tony Tae-Hyoung Kim, Wei Zhang, Chris H. Kim:
An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation. 231-234 - Rony E. Amaya, Cornelius J. Verver:
A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler. 235-238 - Chethan Rao, Alvin Wang, Shaishav Desai:
A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes. 239-242 - Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Wooseok Kim, ByeongHa Park, Chulwoo Kim:
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. 243-246 - Peng Yu, Zheng Gong, Ming Gu, Yin Shi, Foster F. Dai:
A 430MHz-2.15GHz fractional-N frequency synthesizer for DVB and ABS-S applications. 247-250 - Stephen Horst, Stan Phillips, Hossein Miri Lavasani, Farrokh Ayazi, John D. Cressler:
SiGe digital frequency dividers with reduced residual phase noise. 251-254 - Jongsik Kim, Seung Jun Lee, Seungsoo Kim, Jong Ok Ha, Junki Min, Yun Seong Eo, Hyunchol Shin:
A 54-862 MHz CMOS direct conversion transceiver for IEEE 802.22 cognitive radio applications. 255-258 - Yung-Chung Lo, Hsien-Pu Chen, José Silva-Martínez, Sebastian Hoyos:
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. 259-262
Session 9 - Nyquist Rate ADC's
- Eric Naviasky, Ron Kapusta:
Nyquist rate ADCs. - Kailash Chandrashekar, Bertan Bakkaloglu:
A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs. 263-266 - Adrian Leuciuc, William Evans, Honghao Ji, Eric Naviasky, Xinhua He:
A 12-b 56MS/s pipelined ADC in 65nm CMOS. 267-270 - Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, Byeong-Ha Park:
A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. 271-274 - David Gubbins, Sunwoo Kwon, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
A continuous-time input pipeline ADC with inherent anti-alias filtering. 275-278 - Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split capacitor DAC mismatch calibration in successive approximation ADC. 279-282 - Masashi Kijima, Kenji Ito, Kuniyoshi Kamei, Sanroku Tsukamoto:
A 6b 3GS/s flash ADC with background calibration. 283-286 - Jing Yang, Thura Lin Naing, Robert W. Brodersen:
A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS. 287-290
Session 10 - Power Management
- Rajeevan Amirtharajah, Cory Arnold:
Power management. - Charles R. Sullivan:
Integrating magnetics for on-chip power: Challenges and opportunities. 291-298 - Xiaocheng Jing, Philip K. T. Mok, Ming Chak Lee:
A wide-load-range single-inductor-dual-output boost regulator with minimized cross-regulation by constant-charge-auto-hopping (CCAH) control. 299-302 - Weiwei Xu, Ye Li, Xiaohan Gong, Zhiliang Hong, Dirk Killat:
A single-inductor dual-output switching converter with low ripples and improved cross regulation. 303-306 - Ying Wu, Sam Y. S. Tsui, Philip K. T. Mok:
An area- and power-efficient monolithic Buck converter with fast transient response. 307-310 - Xiwen Zhang, Hoi Lee:
An efficiency-enhanced auto-reconfigurable 2x/3x SC charge pump for transcutaneous power transmission. 311-314 - Tatsuya Matano, Koji Sato, Kiyoshi Nakai, Isamu Asano:
A novel on-chip voltage generator for low voltage DRAMs and PRAMs. 315-318
Session 11 - Digital Wireline and PLL Techniques
- Gu-Yeon Wei, Afshin Momtaz:
Digital wireline and PLL techniques. - Amir Bashir, Jing Li, Kiran Ivatury, Naveed Khan, Nirav Gala, Noam Familia, Zulfiqar Mohammed:
Fast lock scheme for phase-locked loops. 319-322 - Chih-Kong Ken Yang, E-Hung Chen:
ADC-based serial I/O receivers. 323-330 - Liangge Xu, Saska Lindfors, Kari Stadius, Jussi Ryynänen:
A 2.4-GHz low-power all-digital phase-locked loop. 331-334 - Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
A nonlinear phase detector for digital phase locked loops. 335-338 - Albert Vareljian, Mohsen Moussavi, William Bereza, Walter Fergusson, Charles E. Berndt, Rakesh H. Patel:
Nonlinear behavior study in digital bang-bang PLL. 339-342 - Yehui Sun, Hui Wang:
Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers. 343-346
Session 12 - Process Integration and Manufacturing Issues
- Philippe Jansen, David A. Sunderland:
Process integration and manufacturing issues. - Stefaan Decoutere, Stefaan Van Huylenbroeck, Bernd Heinemann, Alexander Fox, Pascal Chevalier, Alain Chantre, Thomas F. Meister, Klaus Aufinger, Michael Schröter:
Pushing the speed limits of SiGe: C HBTs up to 0.5 Terahertz. 347-354 - Lloyd W. Condra, Stephan J. Meschter, Dave A. Pinsky, Anthony J. Rafanelli:
The challenge of lead-free electronics for aerospace electronic systems. 355-362 - Raúl Andrés Bianchi, Christine Raynaud, Floria Blanchet, Frederic Monsieur, Olivier Noblanc:
High voltage devices in advanced CMOS technologies. 363-370 - Albert Wang, Patrick R. Gill, Alyosha C. Molnar:
Angle sensitive pixels in CMOS for lensless 3D imaging. 371-374
Session 13 - RF Transceivers and Building Blocks
- John Rogers, Aristotele Hadjichristo:
RF transceivers and building blocks. - Rui Yu, Theng-Tee Yeo, Kwang-Hung Tan, Shouxian Mou, Yike Cui, Haifeng Wang, Hwa-Seng Yap, Eugene Ting, Masaaki Itoh:
A 5.5mA 2.4-GHz two-point modulation Zigbee transmitter with modulation gain calibration. 375-378 - Himanshu Khatri, Prasad S. Gudem, Lawrence E. Larson:
A SAW-less CMOS CDMA receiver with active Tx filtering. 379-382 - Ganesh K. Balachandran, Raymond E. Barnett:
A high dynamic range ASK demodulator for passive UHF RFID with automatic over-voltage protection and detection threshold adjustment. 383-386 - Tyson S. Wooten, Lawrence E. Larson:
A 1 Watt 1-5 GHz Class B push-pull Si/SiGe HBT power amplifier. 387-390 - Behzad Razavi:
Challenges in the design of cognitive radios1. 391-398 - Yonghoon Song, Sungho Lee, Jaejun Lee, Sangwook Nam:
A 29 dBm CMOS class-E power amplifier with 63% PAE using negative capacitance. 399-402 - Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu:
CMOS RF transmitter with integrated power amplifier utilizing digital equalization. 403-406
Session 14 - Micro-Robotics and Energy Harvesting
- Gu Yeon Wu:
Micro-robotics and energy harvesting forum.
Session 15 - Modeling of Passive Elements and Reliability
- Gennady Gildenblat, Hidetoshi Onodera:
Modeling of passive elements and reliability. - Zhiping Yu, Colin C. McAndrew:
RF CMOS is more than CMOS: Modeling of RF passive components. 407-414 - Karthik Balakrishnan, Duane S. Boning:
Measurement and analysis of contact plug resistance variability. 415-422 - Yu Bi, Kees-Jan van der Kolk, Nick van der Meijs:
Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors. 423-426 - Rui Zheng, Jyothi Velamala, Vijay Reddy, Varsha Balakrishnan, Evelyn Mintarno, Subhasish Mitra, Srikanth Krishnan, Yu Cao:
Circuit aging prediction for low-power operation. 427-430 - Tanya Nigam:
Impact of Transistor Level degradation on product reliability. 431-438
Session 16 - 3D ICs and 3D Systems
- Anne Marie Rincon, Alvin Loke:
3D ICs and 3D systems. - Rao R. Tummala, Venky Sundaram, Ritwik Chatterjee, P. Markodeya Raj, Nitesh Kumbhat, Vijay Sukumaran, Vikay Sridharan, Abhishek Choudury, Qiao Chen, Tapobrata Bandyopadhyay:
Trend from ICs to 3D ICs to 3D systems. 439-444 - S. Simon Wong, Abbas El Gamal:
The prospect of 3D-IC. 445-448 - Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. 449-452 - Joy Laskar, Stephane Pinel, Saikat Sarkar, Padmanava Sen, Bevin G. Perumana, Matthew Leung, Debasis Dawn, David Yeh, Francesco Barale, Kevin Chuang, Gopal B. Iyer, Jong-Hoon Lee, Patrick Melet:
60GHz CMOS/PCB co-design and phased array technology. 453-458 - Jeong-Hoon Cho, Hwan-Hee Lee, Jeong-Sik Moon:
The highly integrated mobile WiMAX module using embedded PCB & SIP technology. 459-462 - Roberto Canegallo, Luca Perugini, Alberto Pasini, Massimiliano Innocenti, Mauro Scandiuzzo, Roberto Guerrieri, Pier Luigi Rolandi:
System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface. 463-466
Poster Session
- Edward K. F. Lee:
A 3 - 14V rail-to-rail constant gm opamp in conventional 0.18µm CMOS process. 467-470 - Jens Anders, Paul SanGiorgio, Giovanni Boero:
An integrated CMOS receiver chip for NMR-applications. 471-474 - Jinghua Zhang, Libin Yao, Yong Lian:
A 1.2-V 2.7-mW 160MHz continuous-time delta-sigma modulator with input-feedforward structure. 475-478 - Christopher D. LeBlanc, Benjamin T. Voegeli, Tian Xia:
Dual-loop direct VCO modulation for spread spectrum clock generation. 479-482