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2020 – today
- 2024
[j14]Xin-Yu Shih
, Yu-Chen Lee, Geng-Hong Li, Jia-Han Xie:
High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2349-2353 (2024)- 2023
- [j13]Xin-Yu Shih, Chen-Yen Song, Yao-Yu Lu:
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications. Integr. 93: 102056 (2023) - [j12]Xin-Yu Shih, Yao Chiu, Hsiang-En Wu:
Design and Implementation of Decision-Tree (DT) Online Training Hardware Using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 759-771 (2023) - [j11]Xin-Yu Shih, Hsiang-En Wu, Ming-Xian Cai:
Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5302-5315 (2023) - [c18]Xin-Yu Shih, Lok Hin Samuel Leung, Geng-Hong Li:
Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications. ICCE-Taiwan 2023: 297-298 - 2022
- [j10]Xin-Yu Shih, Jui-Hung Tsai, Bing-Xuan Li, Chi-Ping Huang:
Reconfigurable Hardware Architecture of Area-Efficient Multimode Successive Cancellation (SC) Decoder. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2291-2295 (2022) - [c17]Xin-Yu Shih, Hsiang-En Wu:
Design and Analysis of 7x7 Median Filter with 8-Step Low-Complexity Fast Searching Approach for Undersea Image Processing Applications. ICCE-TW 2022: 89-90 - [c16]Xin-Yu Shih, Chen-Yen Song:
Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching. ICCE-TW 2022: 245-246 - [c15]Xin-Yu Shih, Hsiang-En Wu:
Design Methodology of Queue-Based Fast Classification for Sequential Minimal Optimization in SVM ML-Training. ICCE-TW 2022: 247-248 - [c14]Xin-Yu Shih, Ming-Jyun Wu, Hsiang-En Wu:
A Systematic and Generic Correlation-Based Design Approach for Data Sample Reduction in ML-Training. ICCE-TW 2022: 445-446
2010 – 2019
- 2019
- [j9]Xin-Yu Shih, Hong-Ru Chou:
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. Integr. 64: 40-49 (2019) - [c13]Xin-Yu Shih:
Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications. ICCE-TW 2019: 1-2 - [c12]Xin-Yu Shih:
VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure. ICSAI 2019: 999-1003 - 2018
- [j8]Xin-Yu Shih, Hong-Ru Chou:
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems. ICT Express 4(3): 144-148 (2018) - [j7]Xin-Yu Shih, Po-Chun Huang, Hong-Ru Chou:
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. Integr. 62: 292-300 (2018) - [j6]Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu:
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 118-129 (2018) - [j5]Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu:
Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3942-3955 (2018) - 2017
- [j4]Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou:
48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1456-1467 (2017) - [c11]Xin-Yu Shih, Hong-Ru Chou:
A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems. GCCE 2017: 1-2 - [c10]Xin-Yu Shih, Yue-Qu Liu:
Cost-efficient hardware design of coarse and fine rotation based FFT twiddle factor generator for 3GPP LTE applications. GCCE 2017: 1-2 - [c9]Xin-Yu Shih, Hong-Ru Chou:
Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems. ICCE 2017: 418-419 - 2016
- [c8]Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen:
LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines. APCCAS 2016: 577-580 - [c7]Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu:
Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems. GCCE 2016: 1-2 - [c6]Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen:
High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines. GCCE 2016: 1-2 - 2014
- [j3]Hua Wang, Chun-Hsien Peng, Yaopei Chang, Richard Z. Huang, Chih-Wei Chang, Xin-Yu Shih, Chia-Jui Hsu, Paul C. P. Liang, Ali M. Niknejad, George Chien, Chao Long Tsai, H. C. Hwang:
A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1321-1330 (2014) - 2013
- [c5]Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C. P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, Robert Bogdan Staszewski:
A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. ISSCC 2013: 342-343 - 2012
- [j2]Min-An Chao, Xin-Yu Shih, An-Yeu Wu:
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders. J. Signal Process. Syst. 68(2): 183-202 (2012)
2000 – 2009
- 2009
- [c4]Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu:
A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. ASP-DAC 2009: 121-122 - [c3]Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, An-Yeu Wu:
A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM. ISCAS 2009: 2445-2448 - [c2]Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu:
A Channel-Adaptive Early Termination strategy for LDPC decoders. SiPS 2009: 226-231 - 2008
- [j1]Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu:
An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process. IEEE J. Solid State Circuits 43(3): 672-683 (2008) - [c1]Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu:
High-performance scheduling algorithm for partially parallel LDPC decoder. ICASSP 2008: 3177-3180
Coauthor Index
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