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Yukihide Kohira
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2020 – today
- 2024
- [j18]Masaki Kuramochi
, Yukihide Kohira
, Hiroyoshi Tanabe, Tetsuaki Matsunawa, Chikaaki Kodama
:
Development of a Lithography Simulation Tool Set in Various Optical Conditions for Source Mask Optimization. IEEE Access 12: 58490-58501 (2024) - 2023
- [c21]Yohei Nishidate, Yukihide Kohira, Shigeo Takahashi, Rentaro Yoshioka:
Precise Detection of Changes in Relatively Static Environments for Single-Board Computers. IIAI-AAI 2023: 57-62 - [c20]Shigeo Takahashi, Yohei Nishidate, Yukihide Kohira, Rentaro Yoshioka:
Visualizing Maps of Visitors' Interest for Museum Exhibits with Single-Board Computers. IV 2023: 64-70 - 2022
- [j17]Reon Sato
, Hiroshi Saito
, Yoichi Tomioka
, Yukihide Kohira
:
Energy Reduction Methods for Wild Animal Detection Devices. IEEE Access 10: 24149-24161 (2022) - 2021
- [j16]Yukihide Kohira:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1450 (2021) - [c19]Sho Yatabe, Sora Isobe, Yoichi Tomioka
, Hiroshi Saito, Yukihide Kohira, Qiangfu Zhao:
A CNN Approximation Method Based on Low-bit Quantization and Random Forests. CYBCONF 2021: 39-44 - [c18]Kaisei Kimura, Sho Yatabe, Sora Isobe, Yoichi Tomioka
, Hiroshi Saito, Yukihide Kohira, Qiangfu Zhao:
Area-efficient Binary and Ternary CNN Accelerator using Random-forest-based Approximation. CANDAR 2021: 114-120 - [c17]Keigo Fusaka, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira:
Reliable Night Bear and Boar Detection Based on Training with Pseudo Infrared Images. IIAI-AAI-Winter 2021: 101-110 - [c16]Takayuki Hoshino, Rentaro Yoshioka, Yukihide Kohira:
Design of a Knowledge Experience Based Environment for Museum Data Exploration and Knowledge Creation. MCSoC 2021: 296-303 - 2020
- [j15]Hiroshi Saito, Tatsuki Otake, Hayato Kato, Masayuki Tokutake, Shogo Semba, Yoichi Tomioka
, Yukihide Kohira:
Battery-Powered Wild Animal Detection Nodes with Deep Learning. IEICE Trans. Commun. 103-B(12): 1394-1402 (2020) - [c15]Masayuki Tokutake, Kaisei Shimura, Yoichi Tomioka
, Hiroshi Saito, Yukihide Kohira:
Reliable and Efficient Bear-presence Detection based on Region Proposal of Low-resolution. SMC 2020: 2547-2552
2010 – 2019
- 2019
- [j14]Kota Muroi, Hayato Mashiko, Yukihide Kohira:
Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 894-903 (2019) - 2016
- [j13]Junki Kawaguchi, Hayato Mashiko, Yukihide Kohira:
Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1366-1373 (2016) - [c14]Hayato Mashiko, Yukihide Kohira:
Yield and power improvement method by post-silicon delay tuning and technology mapping. APCCAS 2016: 366-369 - [c13]Yukihide Kohira, Atsushi Takahashi, Tomomi Matsui
, Chikaaki Kodama
, Shigeki Nojima, Satoshi Tanaka:
Manufacturability-aware mask assignment in multiple patterning lithography. APCCAS 2016: 538-541 - 2015
- [c12]Yukihide Kohira, Tomomi Matsui
, Yoko Yokoyama, Chikaaki Kodama
, Atsushi Takahashi
, Shigeki Nojima, Satoshi Tanaka:
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography. ASP-DAC 2015: 665-670 - 2014
- [j12]Hayato Mashiko, Yukihide Kohira:
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2443-2450 (2014) - [j11]Yukihide Kohira, Atsushi Takahashi
:
2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2459-2466 (2014) - [c11]Yukihide Kohira, Atsushi Takahashi
:
2-SAT based linear time optimum two-domain clock skew scheduling. ASP-DAC 2014: 173-178 - [c10]Tomomi Matsui
, Yukihide Kohira, Chikaaki Kodama
, Atsushi Takahashi
:
Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography. ISAAC 2014: 365-375 - [c9]Takahiro Honda, Yukihide Kohira:
An Acceleration for Any-Angle Routing Using Quasi-Newton Method on GPGPU. MCSoC 2014: 281-288 - 2013
- [j10]Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima:
An Effective Overlap Removable Objective for Analytical Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1348-1356 (2013) - [c8]Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima:
An acceleration method by GPGPU for analytical placement using quasi-Newton method. ASICON 2013: 1-4 - 2012
- [c7]Yukihide Kohira, Atsushi Takahashi
:
An any-angle routing method using quasi-Newton method. ASP-DAC 2012: 145-150 - 2011
- [j9]Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi
:
Single-Layer Trunk Routing Using Minimal 45-Degree Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2510-2518 (2011) - 2010
- [j8]Yukihide Kohira, Atsushi Takahashi
:
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2380-2388 (2010) - [c6]Yukihide Kohira, Atsushi Takahashi
:
CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles. ASP-DAC 2010: 281-286
2000 – 2009
- 2009
- [j7]Yukihide Kohira, Shuhei Tani, Atsushi Takahashi
:
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1106-1114 (2009) - [j6]Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi
:
A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2971-2978 (2009) - [j5]Yoichi Tomioka
, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi
:
MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2998-3006 (2009) - [c5]Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi
:
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound. ASP-DAC 2009: 600-605 - 2008
- [j4]Yukihide Kohira, Atsushi Takahashi
:
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(10): 3030-3037 (2008) - [j3]Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
:
A Fast Clock Scheduling for Peak Power Reduction in LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3803-3811 (2008) - [c4]Yukihide Kohira, Shuhei Tani, Atsushi Takahashi
:
Minimization of delay insertion in clock period improvement in general-synchronous framework. APCCAS 2008: 1680-1683 - 2007
- [j2]Yukihide Kohira, Atsushi Takahashi
:
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 800-807 (2007) - [c3]Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
:
A fast clock scheduling for peak power reduction in LSI. ACM Great Lakes Symposium on VLSI 2007: 582-587 - [c2]Yukihide Kohira, Atsushi Takahashi
:
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. ISCAS 2007: 1795-1798 - 2006
- [c1]Yukihide Kohira, Chikaaki Kodama
, Kunihiro Fujiyoshi, Atsushi Takahashi
:
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. ISCAS 2006 - 2005
- [j1]Yukihide Kohira, Atsushi Takahashi
:
Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 892-898 (2005)
Coauthor Index
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last updated on 2024-06-27 20:44 CEST by the dblp team
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