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2020 – today
- 2022
[c12]Joohwan Kim, Junyoung Park, Jindo Byun, Changkyu Seol, Chang Soo Yoon, EunSeok Shin, Hyunyoon Cho, Youngdo Um, Sucheol Lee, Hyungmin Jin, Kwangseob Shin, Hyunsub Norbert Rie, Minsu Jung, Jin-Hee Park, Go-Eun Cha, Minjae Lee, YoungMin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, Hyejeong So, Sungduk Kim, Wansoo Park, Tae Young Kim, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Sang-Hyun Lee:
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process. CICC 2022: 1-2- [c11]Hyunsub Norbert Rie, Chang Soo Yoon, Jindo Byun, Sucheol Lee, Garam Kim, Joohwan Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, Minsu Jung, Go-Eun Cha, Minjae Lee, YoungMin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, EunSeok Shin, Hyuk-Jun Kwon, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application. VLSI Technology and Circuits 2022: 148-149 - 2021
- [c10]Hyungmin Jin, Jindo Byun, Hyunyoon Cho, Hojun Yoon, Jin-Hee Park, Kyoungsoo Kim, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Sang-Hyun Lee:
A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE. A-SSCC 2021: 1-3 - [c9]Hojun Yoon, Wonjoo Jung, Jaewoo Park, Jindo Byun, Hyungmin Jin, Hyunyoon Cho, Youngmin Kim, Baek-Jin Lim, Young-Chul Cho, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Changsik Yoo, Sang-Hyun Lee:
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. ESSCIRC 2021: 463-466 - 2020
- [c8]Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim
, Dukha Park, Kihan Kim, Sang-Yun Kim, Jinsol Park, Hyunyoon Cho, Sukhyun Lim, YeonKyu Choi, Youngil Lim, Daesik Moon, Geuntae Park, Jin-Hun Jang, Kyungho Lee, Isak Hwang, Cheol Kim, Younghoon Son, Gil-Young Kang, Kiwon Park, Seungjun Lee, Su-Yeon Doo, Chang-Ho Shin, Byongwook Na, Ji-Suk Kwon, Kyung Ryun Kim, Hye-In Choi, Seouk-Kyu Choi, Soobong Chang, Wonil Bae, Hyuck-Joon Kwon, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee:
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. ISSCC 2020: 382-384
2010 – 2019
- 2019
- [c7]Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. ISSCC 2019: 378-380 - 2018
- [j3]Sukhan Lee, Hyunyoon Cho, Young Hoon Son, Yuhwan Ro, Nam Sung Kim, Jung Ho Ahn:
Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. IEEE Access 6: 31387-31398 (2018) - 2017
- [j2]Young Hoon Son, Hyunyoon Cho, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn:
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. IEEE Comput. Archit. Lett. 16(1): 76-79 (2017) - [c6]Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. A-SSCC 2017: 153-156 - [c5]Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim:
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. HPCA 2017: 61-72 - [c4]Yuhwan Ro, Hyunyoon Cho, Eojin Lee, Daejin Jung, Young Hoon Son, Jung Ho Ahn, Jae W. Lee:
SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. HPCA 2017: 517-528 - [c3]Sukhan Lee, Yuhwan Ro, Young Hoon Son, Hyunyoon Cho, Nam Sung Kim, Jung Ho Ahn:
Understanding power-performance relationship of energy-efficient modern DRAM devices. IISWC 2017: 110-111 - 2012
- [j1]Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo-Sun Choi, Young-Hyun Jun:
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. IEEE J. Solid State Circuits 47(1): 107-116 (2012) - [c2]Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung-Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Young Hoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. ISSCC 2012: 44-46 - 2011
- [c1]Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun:
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. ISSCC 2011: 496-498
Coauthor Index
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