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Journal Articles
- 2024
[j31]Kashif Inayat
, Inayat Ullah, Jaeyong Chung:
Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1205-1215 (2024)- 2022
- [j30]Kashif Inayat, Jaeyong Chung:
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration. IEEE Trans. Very Large Scale Integr. Syst. 30(7): 881-892 (2022) - 2021
- [j29]Phuoc Pham, Jacob A. Abraham, Jaeyong Chung:
Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer. IEEE Access 9: 47194-47203 (2021) - 2020
- [j28]Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang:
Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits. IEEE Access 8: 42231-42242 (2020) - [j27]Inayat Ullah, Joon-Sung Yang, Jaeyong Chung:
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1084-1088 (2020) - 2019
- [j26]Woochul Kang, Jaeyong Chung:
Power- and Time-Aware Deep Learning Inference for Mobile Embedded Devices. IEEE Access 7: 3778-3789 (2019) - [j25]Pilyeong Jeong, Mungyeong Choe, Nahyeong Kim, Jaehyun Park, Jaeyong Chung:
Physical Workout Classification Using Wrist Accelerometer Data by Deep Convolutional Neural Networks. IEEE Access 7: 182406-182414 (2019) - [j24]Woochul Kang, Jaeyong Chung:
DeepRT: predictable deep learning inference for cyber-physical systems. Real Time Syst. 55(1): 106-135 (2019) - [j23]Jaeyong Chung, Taehwan Shin, Joon-Sung Yang:
Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2032-2042 (2019) - [j22]Yongshin Kang, Joon-Sung Yang, Jaeyong Chung:
Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2167-2171 (2019) - 2018
- [j21]Byung-Su Kim, Tae Hee Han, Joon-Sung Yang, Jaeyong Chung:
New library development method by FSM based cell pattern extraction. IEICE Electron. Express 15(9): 20171226 (2018) - [j20]Yongshin Kang, Jaeyong Chung:
Dynamic Fixed-Point Design of Neuromorphic Computing Systems. IEICE Trans. Electron. 101-C(10): 840-844 (2018) - [j19]Sae-Eun Kim, Jaeyong Chung, Joon-Sung Yang:
Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning. IEEE Trans. Computers 67(8): 1184-1192 (2018) - [j18]Hyunseung Han, Jaeyong Chung, Joon-Sung Yang:
READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution. IEEE Trans. Computers 67(8): 1193-1201 (2018) - 2017
- [j17]Jaeyong Chung, Woochul Kang:
Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems. IEICE Trans. Electron. 100-C(11): 1073-1076 (2017) - [j16]Woochul Kang, Jaeyong Chung:
Energy-efficient response time management for embedded databases. Real Time Syst. 53(2): 228-253 (2017) - 2016
- [j15]Jaeyong Chung, Woochul Kang:
Defect Diagnosis via Segment Delay Learning. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 388-392 (2016) - 2015
- [j14]Jibum Kim, Jaeyong Chung:
Untangling polygonal and polyhedral meshes via mesh optimization. Eng. Comput. 31(3): 617-629 (2015) - [j13]Eun Jung Jang, Jaeyong Chung, Jacob A. Abraham:
Delay Defect Diagnosis Methodology Using Path Delay Measurements. IEICE Trans. Electron. 98-C(10): 991-994 (2015) - [j12]Woochul Kang, Jaeyong Chung:
QoS Management for Embedded Databases in Multicore-Based Embedded Systems. Mob. Inf. Syst. 2015: 657252:1-657252:14 (2015) - [j11]Jaeyong Chung, Lok-Won Kim:
Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems. IEEE Trans. Computers 64(11): 3091-3101 (2015) - [j10]Jaeyong Chung, Jibum Kim:
Segment Delay Learning From Quantized Path Delay Measurements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 1038-1042 (2015) - 2014
- [j9]Jaeyong Chung, Yonghyun Kim, Joon-Sung Yang:
3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2005-2009 (2014) - 2013
- [j8]Jaeyong Chung, Joonsung Park, Jacob A. Abraham:
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 281-291 (2013) - [j7]Jaeyong Chung, Jacob A. Abraham:
Concurrent Path Selection Algorithm in Statistical Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1715-1726 (2013) - 2012
- [j6]Jaeyong Chung, Henry J. Gardner:
Temporal Presence Variation in Immersive Computer Games. Int. J. Hum. Comput. Interact. 28(8): 511-529 (2012) - [j5]Jaeyong Chung, Jacob A. Abraham:
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 485-496 (2012) - [j4]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 497-508 (2012) - [j3]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Testability-Driven Statistical Path Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1275-1287 (2012) - [j2]Jaeyong Chung, Jacob A. Abraham:
On Computing Criticality in Refactored Timing Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1935-1939 (2012) - 2011
- [j1]Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, Jacob A. Abraham:
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. J. Electron. Test. 27(4): 429-439 (2011)
Conference and Workshop Papers
- 2023
- [c22]Tayyeb Mahmood, Kashif Inayat, Jaeyong Chung:
Quickloop: An Efficient, FPGA-Accelerated Exploration of Parameterized DNN Accelerators. PACT 2023: 327-328 - [c21]Phuoc Pham, Jaeyong Chung:
AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing. DAC 2023: 1-6 - 2020
- [c20]Inayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung:
Factored Radix-8 Systolic Array for Tensor Processing. DAC 2020: 1-6 - [c19]Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang:
Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture. DATE 2020: 352-357 - 2017
- [c18]Seban Kim, Jaeyong Chung:
Synthesis of activation-parallel convolution structures for neuromorphic architectures. DATE 2017: 1685-1690 - [c17]Yongshin Kang, Jaeyong Chung:
A dynamic fixed-point representation for neuromorphic computing systems. ISOCC 2017: 44-45 - 2016
- [c16]Jaeyong Chung, Taehwan Shin:
Simplifying deep neural networks for neuromorphic architectures. DAC 2016: 126:1-126:6 - [c15]Taehwan Shin, Yongshin Kang, Seungho Yang, Seban Kim, Jaeyong Chung:
Live demonstration: Real-time image classification on a neuromorphic computing system with zero off-chip memory access. ISCAS 2016: 449 - 2011
- [c14]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Path criticality computation in parameterized statistical timing analysis. ASP-DAC 2011: 249-254 - [c13]Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham:
Post-Silicon Timing Validation Method Using Path Delay Measurements. Asian Test Symposium 2011: 232-237 - [c12]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Testability driven statistical path selection. DAC 2011: 417-422 - 2010
- [c11]Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh:
At-speed Test of High-Speed DUT Using Built-Off Test Interface. Asian Test Symposium 2010: 269-274 - [c10]Hyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo:
A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. ETS 2010: 145-150 - [c9]Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo:
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate. VTS 2010: 33-38 - 2009
- [c8]Joonsung Park, Jaeyong Chung, Jacob A. Abraham:
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. Asian Test Symposium 2009: 373-378 - [c7]Jaeyong Chung, Jacob A. Abraham:
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. ICCAD 2009: 321-327 - [c6]Jaeyong Chung, Henry J. Gardner:
Measuring temporal variation in presence during game playing. VRCAI 2009: 163-168 - [c5]Jaeyong Chung, Jacob A. Abraham:
Recursive Path Selection for Delay Fault Testing. VTS 2009: 65-70 - 2006
- [c4]Jaeyong Chung, Kwanghyun Shim:
Color Object Tracking System for Interactive Entertainment Applications. ICASSP (5) 2006: 497-500 - [c3]Jungyoul Lim, Jaeyong Chung, Jin Ryong Kim, Kwanghyun Shim:
A Dynamic Load Balancing for Massive Multiplayer Online Game Server. ICEC 2006: 239-249 - 2004
- [c2]YungWoo Jung, Bum-Hyun Lim, Kwanghyun Sim, Hunjoo Lee, Ilkyu Park, Jaeyong Chung, Jihong Lee:
VENUS: The Online Game Simulator Using Massively Virtual Clients. AsiaSim 2004: 589-596 - 2003
- [c1]Jaeyong Chung, Gwanghyun Shim, Byungtae Choi:
Driving Virtual Human using the Hybrid of Position-based and Angle-based Control Mode. Modelling, Simulation, and Optimization 2003: 194-199
Informal and Other Publications
- 2021
- [i2]Phuoc Pham, Jacob A. Abraham, Jaeyong Chung:
Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric Quantizer. CoRR abs/2104.00210 (2021) - 2015
- [i1]Jaeyong Chung, Taehwan Shin, Yongshin Kang:
INsight: A Neuromorphic Computing System for Evaluation of Large Neural Networks. CoRR abs/1508.01008 (2015)
Coauthor Index
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last updated on 2024-08-05 20:20 CEST by the dblp team
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