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ORCIDVTS 2009: Santa Cruz, CA, USA
- 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA. IEEE Computer Society 2009, ISBN 978-0-7695-3598-2
- Thomas A. Ziaja, Poh J. Tan:
Efficient Array Characterization in the UltraSPARC T2. 3-8 - Michail Maniatakos
, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris:
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. 9-14 - Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li:
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. 15-20 - Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker:
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. 21-26 - Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo:
Small Delay Fault Model for Intra-Gate Resistive Open Defects. 27-32 - Haluk Konuk:
Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip-Flop Testing. 33-38 - Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Soft-Error Hardening Designs of Nanoscale CMOS Latches. 41-46 - Rudrajit Datta, Nur A. Touba:
Exploiting Unused Spare Columns to Improve Memory ECC. 47-52 - Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu:
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. 53-58 - Zheng Wang, Duncan M. Hank Walker:
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric. 59-64 - Jaeyong Chung, Jacob A. Abraham:
Recursive Path Selection for Delay Fault Testing. 65-70 - Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. 71-76 - Joon-Sung Yang, Nur A. Touba:
Automated Selection of Signals to Observe for Efficient Silicon Debug. 79-84 - Jianliang Gao, Yinhe Han, Xiaowei Li:
A New Post-Silicon Debug Approach Based on Suspect Window. 85-90 - Richard McLaughlin, Srikanth Venkataraman, Carlston Lim:
Automated Debug of Speed Path Failures Using Functional Tests. 91-96 - Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal:
Output Hazard-Free Transition Delay Fault Test Generation. 97-102 - Kun Young Chung, Sandeep K. Gupta:
Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. 103-110 - Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia:
Effective and Efficient Test Pattern Generation for Small Delay Defect. 111-116 - Kee Sup Kim:
Panel: Apprentice - VTS Edition: Season 2. 119 - Haluk Konuk:
DFT and Test Problems from the Trenches. 120 - Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu:
Multiple-Fault Diagnosis Using Faulty-Region Identification. 123-128 - Kay Suenaga, Sebastià A. Bota, Rodrigo Picos, Eugeni Isern, Miquel Roca, Eugenio García-Moreno:
Predictive Test Technique for Diagnosis of RF CMOS Receivers. 129-133 - Xiaochun Yu, Yen-Tzu Lin, Wing Chiu Tam, Osei Poku, Ronald D. Blanton:
Controlling DPPM through Volume Diagnosis. 134-139 - Edward Flanigan, Spyros Tragoudas, Arkan Abdulrahman:
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions. 140-145 - Zhen Chen, Dong Xiang, Boxue Yin:
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost. 146-151 - Sunghoon Chun, YongJoon Kim, Taejin Kim, Sungho Kang:
A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections. 152-157 - Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar:
False Path Aware Timing Yield Estimation under Variability. 161-166 - Ritesh P. Turakhia, Mark Ward, Sandeep Kumar Goel, Brady Benware:
Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study. 167-172 - Saeed Shamshiri, Kwang-Ting Cheng:
Yield and Cost Analysis of a Reliable NoC. 173-178 - Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz:
Restrict Encoding for Mixed-Mode BIST. 179-184 - Keith A. Jenkins, Lionel Li:
A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset. 185-188 - Livier Lizarraga, Salvador Mir, Gilles Sicard:
Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors. 189-194 - Yen-Tzu Lin, Chukwuemeka U. Ezekwe, Ronald D. Blanton:
Physically-Aware N-Detect Test Relaxation. 197-202 - Tao Lv, Huawei Li, Xiaowei Li:
Automatic Selection of Internal Observation Signals for Design Verification. 203-208 - Ajay Khoche, Jay Katz, Sauro Landini, Kochen Liao, Neetu Agrawal, Glenn Plowman, Songlin Zuo, Liyang Lai, John Rowe, Thomas Zanon:
STDF Memory Fail Datalog Standard. 209-214 - A. Hakan Baba, Subhasish Mitra:
Testing for Transistor Aging. 215-220 - Junxia Ma, Jeremy Lee, Mohammad Tehranipoor:
Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths. 221-226 - Pankaj Pant, Joshua Zelman:
Understanding Power Supply Droop during At-Speed Scan Testing. 227-232 - Yiorgos Makris, Haralampos-G. D. Stratigopoulos:
Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest. 233 - Bernard Courtois, Chandu Visweswariah:
Special Session 8: New Topics: At-Speed Testing in the Face of Process Variations. 237 - Bernard Courtois, Ali Shakouri:
Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips. 241 - Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
Highly X-Tolerant Selective Compaction of Test Responses. 245-250 - Dong Xiang, Boxue Yin, Kwang-Ting Cheng:
Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure. 251-256 - Sounil Biswas, Ronald D. Blanton:
Maintaining Accuracy of Test Compaction through Adaptive Re-learning. 257-263 - Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti:
RT-Level Deviation-Based Grading of Functional Test Sequences. 264-269 - Naveen Velamati, Robert Daasch:
Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering. 270-275 - Davide Appello, Paolo Bernardi, Simone Gerardin, Michelangelo Grosso, Alessandro Paccagnella, Paolo Rech, Matteo Sonza Reorda:
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study. 276-281 - Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector. 285-290 - Hsiu-Ming Chang, Chin-Hsuan Chen, Kuan-Yu Lin, Kwang-Ting Cheng:
Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC. 291-296 - Kenneth Blakkan, Mani Soma:
A Time Domain Method to Measure Oscillator Phase Noise. 297-302 - Erdem Serkan Erdogan, Sule Ozev:
A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources. 303-308 - Tao Xu, Krishnendu Chakrabarty:
Design-for-Testability for Digital Microfluidic Biochips. 309-314 - Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura:
Stuck-Open Fault Leakage and Testing in Nanometer Technologies. 315-320 - Unni Chandran, Dan Zhao:
SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration. 321-326 - Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin:
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. 327-332 - Bhanu Kapoor:
Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and Testing. 333 - Arani Sinha, Amitava Majumdar, Vasu Ganti:
Panel: Analog Characterization and Test: The Long Road to Realization. 337 - Andrew Piziali:
Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough? 338
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