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ORCIDKatarzyna Radecka
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2020 – today
- 2022
[j15]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Wearable Vibrotactile System as an Assistive Technology Solution. Mob. Networks Appl. 27(2): 709-717 (2022)
2010 – 2019
- 2019
- [c49]Jianing Sun, Katarzyna Radecka, Zeljko Zilic:
Exploring Better Food Detection via Transfer Learning. MVA 2019: 1-6 - [i1]Jianing Sun, Katarzyna Radecka, Zeljko Zilic:
FoodTracker: A Real-time Food Detection Mobile Application by Deep Convolutional Neural Networks. CoRR abs/1909.05994 (2019) - 2017
- [j14]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
A Comprehensive Analysis on Wearable Acceleration Sensors in Human Activity Recognition. Sensors 17(3): 529 (2017) - [c48]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Designing and Evaluating a Vibrotactile Language for Sensory Substitution Systems. MobiHealth 2017: 58-66 - [c47]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
A Novel Algorithm to Reduce Machine Learning Efforts in Real-Time Sensor Data Analysis. MobiHealth 2017: 83-90 - 2016
- [j13]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Respiration Disorders Classification With Informative Features for m-Health Applications. IEEE J. Biomed. Health Informatics 20(3): 733-747 (2016) - [c46]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Haptic feedback and human performance in a wearable sensor system. BHI 2016: 620-624 - 2015
- [j12]Yu Pang, Yafeng Yan, Jinzhao Lin, Guoquan Li, Huawei Huang, Lei Shi, Katarzyna Radecka:
ICAT: Engine to Perform Range Analysis and Allocate Bit-Widths for Arithmetic Datapaths. J. Circuits Syst. Comput. 24(2): 1550020:1-1550020:28 (2015) - [j11]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Movement analysis of the chest compartments and a real-time quality feedback during breathing therapy. Netw. Model. Anal. Health Informatics Bioinform. 4(1): 21 (2015) - [j10]Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Design and Evaluation of an Intelligent Remote Tidal Volume Variability Monitoring System in E-Health Applications. IEEE J. Biomed. Health Informatics 19(5): 1532-1548 (2015) - 2014
- [j9]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders. Sensors 14(6): 11204-11224 (2014) - [c45]Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. BIBE 2014: 141-148 - [c44]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Multi-sensor blind recalibration in mHealth applications. IHTC 2014: 1-4 - [c43]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Affordable erehabilitation monitoring platform. IHTC 2014: 1-6 - [c42]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Development of a Remote Monitoring System for Respiratory Analysis. IoT360 (1) 2014: 193-202 - [c41]Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Tidal volume variability and respiration rate estimation using a wearable accelerometer sensor. MobiHealth 2014: 1-6 - [c40]Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Automated diagnosis of knee pathology using sensory data. MobiHealth 2014: 95-98 - [c39]Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic:
A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications. NEWCAS 2014: 37-40 - 2013
- [j8]Omid Sarbishei, Katarzyna Radecka:
On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 831-844 (2013) - [c38]Yu Pang, Qian Lei, Jinzhao Lin, Zhiyong Luo, Zhangyong Li, Zeljko Zilic, Katarzyna Radecka:
SAR Computation and Channel Modeling of Body Area Network. BODYNETS 2013: 120-123 - [c37]Omid Sarbishei, Benjamin Nahill, Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic, Boris Karajica:
An efficient fault-tolerant sensor fusion algorithm for accelerometers. BSN 2013: 1-6 - [c36]Omid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka:
A minimum MSE sensor fusion algorithm with tolerance to multiple faults. ETS 2013: 1 - [c35]Sayeeda Sultana, Katarzyna Radecka:
Testing reversible adder/subtractor for missing control points. MWSCAS 2013: 412-415 - [c34]Sayeeda Sultana, Atena Roshan Fekr, Katarzyna Radecka:
SAT-based reversible gate/wire replacement fault testing. MWSCAS 2013: 1075-1078 - 2012
- [j7]Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic:
Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 343-355 (2012) - [c33]Omid Sarbishei, Katarzyna Radecka:
Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. ASP-DAC 2012: 789-794 - [c32]Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic:
MSE minimization and fault-tolerant data fusion for multi-sensor systems. ICCD 2012: 445-452 - [c31]Omid Sarbishei, Katarzyna Radecka:
Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT). ISCAS 2012: 592-595 - [c30]Majid Janidarmian, Zeljko Zilic, Katarzyna Radecka:
Issues in Multi-valued Multi-modal Sensor Fusion. ISMVL 2012: 238-243 - 2011
- [c29]Omid Sarbishei, Katarzyna Radecka:
On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers. IEEE Symposium on Computer Arithmetic 2011: 62-69 - [c28]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. ASP-DAC 2011: 455-460 - [c27]Sayeeda Sultana, Katarzyna Radecka, Yu Pang:
A study on relating redundancy removal in classical circuits to reversible mapping. ICCD 2011: 206-211 - [c26]Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka:
Positive Davio-based synthesis algorithm for reversible logic. ICCD 2011: 212-218 - [c25]Sayeeda Sultana, Katarzyna Radecka:
Reversible implementation of square-root circuit. ICECS 2011: 141-144 - [c24]Omid Sarbishei, Katarzyna Radecka:
Analysis of Mean-Square-Error (MSE) for fixed-point FFT units. ISCAS 2011: 1732-1735 - [c23]Yu Pang, Katarzyna Radecka:
An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking. ISCAS 2011: 1736-1739 - [c22]Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka:
A novel method of synthesizing reversible logic. ISCAS 2011: 2857-2860 - [c21]Sayeeda Sultana, Katarzyna Radecka:
Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. ISMVL 2011: 147-152 - [c20]Zeljko Zilic, Katarzyna Radecka:
Fault tolerant glucose sensor readout and recalibration. Wireless Health 2011: 35 - 2010
- [j6]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1177-1190 (2010) - [c19]Omid Sarbishei, Yu Pang, Katarzyna Radecka:
Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. HLDVT 2010: 25-32 - [c18]Omid Sarbishei, Katarzyna Radecka:
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. ICCAD 2010: 739-745 - [c17]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
An efficient method to perform range analysis for DSP circuits. ICECS 2010: 855-858
2000 – 2009
- 2008
- [j5]Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka:
Design for Testability of QCA Logic Under Stuck-at-value Fault Model. J. Multiple Valued Log. Soft Comput. 14(1-2): 145-176 (2008) - [c16]Yu Pang, Katarzyna Radecka:
Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. DAC 2008: 397-402 - 2007
- [j4]Ali Khazamipour, Katarzyna Radecka:
Adiabatic Implementation of Reversible Logic Circuits in CMOS Technology. J. Multiple Valued Log. Soft Comput. 13(1-2): 191-216 (2007) - [j3]Zeljko Zilic, Katarzyna Radecka:
Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers 56(2): 202-207 (2007) - [c15]Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur:
Reversible circuit technology mapping from non-reversible specifications. DATE 2007: 558-563 - 2006
- [c14]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Algorithms for Compositions of Arithmetic Transforms and Their Extensions. ICECS 2006: 379-382 - [c13]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion. ICECS 2006: 696-699 - [c12]Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka:
Testing QCA Modular Logic. ICECS 2006: 700-703 - [c11]Rong Zhang, Zeljko Zilic, Katarzyna Radecka:
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS 2006: 186-191 - 2004
- [j2]Katarzyna Radecka, Zeljko Zilic:
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers 53(5): 628-640 (2004) - [c10]Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka:
FPGA Emulation of Quantum Circuits. ICCD 2004: 310-315 - [c9]Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka:
Architectures of Increased Availability Wireless Sensor Network Nodes. ITC 2004: 1232-1241 - 2002
- [c8]Katarzyna Radecka, Zeljko Zilic:
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD 2002: 128-131 - [c7]Zeljko Zilic, Katarzyna Radecka:
The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL 2002: 129-135 - [c6]Katarzyna Radecka, Zeljko Zilic:
Identifying Redundant Wire Replacements for Synthesis and Verification. ASP-DAC/VLSI Design 2002: 517-523 - 2001
- [c5]Katarzyna Radecka, Zeljko Zilic:
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD 2001: 348-353 - [c4]Katarzyna Radecka, Zeljko Zilic, Karim Khordoc:
Combinational verification by simulations, SAT and BDDs. ICECS 2001: 1627-1630 - [c3]Zeljko Zilic, Katarzyna Radecka:
: Identifying redundant gate replacements in verification by error modeling. ITC 2001: 803-812 - 2000
- [c2]Katarzyna Radecka, Zeljko Zilic:
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS 2000: 271-280
1990 – 1999
- 1999
- [c1]Zeljko Zilic, Katarzyna Radecka:
On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC 1999: 67-74 - 1997
- [j1]Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer:
Arithmetic built-in self-test for DSP cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1358-1369 (1997)
Coauthor Index
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