DATE 2007: Nice, France

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Design records

Design for testability for SoCs

Communication synthesis under timing constraints

Performance modelling and synthesis of analogue/mixed-signal circuits

System level mapping and simulation

Algorithms and applications of run-time reconfiguration

IP designs for media processing and other computational intensive kernels

Test infrastructure of SoCs and its verification

Hot topic - Microprocessors in the era of terascale integration

Statistical/nonlinear analysis and verification for analogue circuits

System modeling and specification

Design space exploration and nano-technologies for reconfigurable computing

Implementation of LDPC codecs for various communication standards

Testing NoCs

Synthesis at system and architectural levels

Analogue and mixed-signal design and characterization

Should you trust the surgeon or the family doctor?

Automatic synthesis of computation intensive application specific circuits

Embedded tutorial


Test generation for diagnosis, scan testing and advanced memory fault models

Future design challenges

Application-specific architectures

Technology and process aware low power circuit design

Hardware implementation of MPSoCs and NoCs architectures