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ORCID8th ICECS 2001: Malta
- Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001. IEEE 2001, ISBN 0-7803-7057-0
- Dennis D. Buss:
Si technology in the Internet Era. 1-4 - Sanjit K. Mitra:
Circuits and signal processing: accomplishments and future trends. 5 - Eric Soenen:
Technology tradeoffs in the design of high performance analog to digital converters. 7-11 - Mario Paparo:
Power management systems on silicon for portable equipment. 13-18 - Siew Kuok Hoon, Ugur Çilingiroglu:
An optimally self-biased threshold-voltage extractor. 19-22 - Monica Finsrud, Mats Høvin, Tor Sverre Lande:
Second order MASH Δ ΣFDM-solution with adaptive improvements. 23-26 - Srdjan Dragic, Igor M. Filanovsky, Martin Margala:
A novel wide-band CMOS current amplifying cell and its application in power supply current monitoring. 27-30 - Johan van der Tang, Cicero S. Vaucher:
Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters. 31-34 - Christos Drosos, Chrissavgi Dre, Dimitris Metafas, Dimitrios Soudris, Spyros Blionas:
The low power baseband processing parts of a novel dual mode DECT/GSM terminal. 35-38 - Luca Fanucci, Roberto Roncella
, Roberto Saletti:
Efficient sine evaluation architecture for direct digital frequency synthesis. 39-42 - Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang:
A difference detector PFD for low jitter PLL. 43-46 - L. Camino, Serge Ramet, Jean-Baptiste Bégueret, Yann Deval, Pascal Fouillat:
Phase error determination in GMSK modulated fractional-N PLL. 47-50 - Florean Curticapean, Jarkko Niittylahti:
A hardware efficient direct digital frequency synthesizer. 51-54 - Chao Xu, Winslow Sargeant, Kenneth R. Laker, Jan Van der Spiegel:
Fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and 35 ps jitter. 55-58 - Oscar Gustafsson, Lars Wanhammar:
Decreasing the minimal sample period for recursive filters implemented using distributed arithmetic. 59-62 - Ewa Hermanowicz:
Estimation of samples of the derivative of a signal based on the signal difference derivative. 63-66 - Marcelino Lázaro, Ignacio Santamaría, Carlos Pantaleón:
A regularized digital filtering technique for the simultaneous reconstruction of a function and its derivatives. 67-70 - Henrik Ohlsson, Oscar Gustafsson, Håkan Johansson, Lars Wanhammar:
Implementation of bit-parallel lattice wave digital filters with increased maximal sample rate. 71-74 - Adrian Burian, Jukka Saarinen, Pauli Kuosmanen:
Multi-window recursive adaptive neural filters. 75-78 - Hisato Fujisaka, Maki Akita, Mititada Morisue:
Dynamical intelligent network based on group representation theory. 79-82 - José Manoel de Seixas, D. O. Damázio, Paulo S. R. Diniz, W. Soares-Fillho:
Wavelet transform as a preprocessing method for neural classification of passive sonar signals. 83-86 - Philipp Häfliger:
Asynchronous event redirecting in bio-inspired communication. 87-90 - Pilar Jarabo Amores, Manuel Rosa-Zurera, Francisco López-Ferreras, Manuel Utrilla-Manso:
Time-frequency analysis as a tool for improving neural detectors for low probability of false alarm. 91-94 - Xu Jingnan, J. Serras, M. Oliveira, R. Belo, M. Bugalho, João C. Vital, Nuno Horta, José E. Franca:
IC design automation from circuit level optimization to retargetable layout. 95-98 - Alexander Zemliak:
Analog system design problem formulation on the basis of control theory. 99-102 - Salih Günes, Nihat Yilmaz, Ercan Yaldiz:
Fault tolerant unicast routing algorithm based on parallel branching method for faulty hypercube. 103-106 - Christian Paulus, Ralf Brederlow, Ulrich Kleine, Roland Thewes:
An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits. 107-111 - Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh:
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. 113-116 - Michael Fischell, Walter Anheier:
Investigations of on-line/off-line tests for sensors. 117-120 - A. A. Nassiopoulos, G. Kaltsas, A. G. Nassiopoulou:
Stabilization of power consumption of the heater of a micromachined silicon gas flow sensor. 121-124 - Chung-Yu Wu, Kuan-Hsun Huang, Li-Ju Lin:
The design of CMOS real-time motion-direction detection chip with BJT-based silicon-retina sensors and correlation-based motion detection algorithm. 125-128 - Vincent Frick, Luc Hébrard, Philippe Poure, Francis Braun:
CMOS microsystem front-end for microtesla resolution magnetic field measurement. 129-132 - António J. Gano, Nuno F. Especial:
Fully differential CMOS programmable analogue sensor interface based on fully differential multiple differences amplifiers. 133-136 - Enrico Dallago, Marco Passoni, Giuseppe Venchi:
Boost-type power factor correction system with three-level sigma-delta modulation. 137-140 - Karl H. Edelmoser, Felix A. Himmelstoss:
Control strategy of a solar power inverter (analysis of a seventh order system). 141-144 - Cyril Spiteri Staines, Joseph Cilia:
Sensorless position estimation using asymmetries in A.C. machines. 145-148 - Predrag Ninkovic, Zarko Janda:
Minimum settling time voltage regulation of single-phase PFC converters. 149-152 - Malik Elbuluk, Scott Gerber, Ahmad Hammoud, Richard L. Patterson:
Performance of power converters at cryogenic temperatures. 153-156 - Jan Vondras, Pravoslav Martinek:
New approach to analog filters and group delay equaliser transfer function design. 157-160 - Eric Kerhervé, Mathieu Hazouard, Pierre Jarry:
The real-frequency technique applied to a narrow band MMIC active filter with transmission zero at finite frequencies. 161-164 - Ali Toker, Ece Olcay Günes, Serdar Özoguz:
New high-Q band-pass filter configuration using current controlled current conveyor based all-pass filters. 165-168 - Antônio Carlos M. de Queiroz:
A simple design technique for multiple resonance networks. 169-172 - Ugur Çilingiroglu, Luthuli Edem Dake:
A sampled-analog rank-order-filter architecture. 173-176 - Fengqi Yu, Alan N. Willson Jr.:
Multirate digital squarer architectures. 177-180 - Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise. 181-184 - Roelof H. Klunder, Jaap Hoekstra:
Programmable logic using a SET electron box. 185-188 - Troy A. Johnson, Ivan S. Kourtev:
A single latch, high speed double-edge triggered flip-flop (DETFF). 189-192 - Antonio G. M. Strollo, Ettore Napoli, Davide De Caro:
New design of squarer circuits using Booth encoding and folding techniques. 193-196 - Marcello Pesare, Agostino Giorgio, Anna Gina Perri:
A method to determine the thermal dependence of large and small signal equivalent circuit parameters of GaAs FETs. 197-200 - Franco L. Fiori, Paolo Stefano Crovetti:
Nonlinear effects of RF interference in MOS operational amplifiers. 201-204 - Arturo Sarmiento-Reyes, Luis Hernández-Martínez, Héctor Vázquez-Leal:
A topological approach for determining the uniqueness of the DC solutions in MOS-transistor circuits. 205-208 - Gaetano Palumbo, Salvatore Pennisi:
Feedback amplifiers: a simplified analysis of harmonic distortion in the frequency domain. 209-212 - Miguel A. Vega-Rodríguez, Juan M. Sánchez-Pérez, Juan Antonio Gómez Pulido:
Real time image processing with reconfigurable hardware. 213-216 - Donglai Xu, John P. Bentley:
VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding. 217-220 - Atoosa Masoudnia, Hamid Sarbazi-Azad, Said Boussakta:
A FIFO-based architecture for high speed image compression. 221-224 - Wael M. Badawy:
An SIMD architecture for texture mapping. 225-228 - Amar Aggoun, I. Jalloh:
A parallel 3D DCT architecture for the compression of integral 3D images. 229-232 - Chua-Chin Wang, Chih-Chiang Chiu, Yu-Tsung Chien:
Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs. 233-236 - J. C. Rau, J. H. Wang, S. C. Chang:
Logic optimization of circuits with pre-defined internal don't cares. 237-240 - Walter Lange, Wolfgang Rosenstiel:
Synthesis of data transmission circuits starting from behavioral HW descriptions. 241-244 - Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
I/O buffer placement methodology for ASICs. 245-248 - Dingjun Chen, Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi:
Distributed evolutionary design of constant-coefficient multipliers. 249-252 - Marios Iliopoulos, Theodore Antonakopoulos:
Optimised reconfigurable MAC processor architecture. 253-258 - Badreddine Rejeb, Heiko Henkelmann, Walter Anheier:
Integer division in residue number system. 259-262 - Shugang Wei, Kensuke Shimizu:
Fast residue arithmetic multipliers based on signed-digit number system. 263-266 - Nobuhiro Tomabechi, Teruki Ito:
Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers. 267-271 - Omar Nibouche, Ahmed Bouridane, Mokhtar Nibouche:
Bit-level architectures for Montgomery's multiplication. 273-276 - Marco Grangetto, Enrico Magli, Gabriella Olmo:
Unequal processing gain for JPEG2000 image transmission in a CDMA environment. 277-280 - Kilian A. Jacob:
MPEG-4 Main Profile decoder partitioning with respect to bit stream processing. 281-284 - Kostas Masselos, Francky Catthoor, A. Kakarudas, Costas E. Goutis, Hugo De Man:
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures. 285-288 - Weiguo Zheng, Ishfaq Ahmad, Ming Lei Liou:
Benchmark the software based MPEG-4 video codec. 289-292 - Krzysztof Wawryn, Bogdan Strzeszewski:
Current mode AB class WTA circuit. 293-296 - Ana Rusu, Serban Lungu:
Modeling and simulation of low-power and low-voltage delta-sigma modulators. 297-300 - Isao Hishinuma:
Collapse of lost solution and chaos in a driven piecewise linear Rayleigh oscillator. 301-304 - Patricia Desgreys, Patrick Loumeau:
Evolution of SI circuit performances with technological advances. 305-308 - Valery Zagursky:
Method for testing and characterization of analog-digital systems. 309-312 - Yuri Bruck:
About linearization of broadband amplifier by feedback (new opportunity of the well known method). 313-316 - Chun Lai Yiu, Philip K. T. Mok:
Design of polysilicon TFT operational amplifier for analog TFT AMLCD driver. 317-320 - Maurits Ortmanns, Friedel Gerfers, Lourans Samid, Yiannos Manoli:
Successful design of cascaded continuous-time ΣΔ modulators. 321-324 - Sang Chan Han, Bum Soo Suh, Soo Won Kim:
A two-step folder for a high-speed CMOS folding-and-interpolating ADC. 325-328 - Kari Stadius, Petri Järviö, Kari Halonen:
A novel BJT output stage for SAW drivers. 329-332 - Tae-Ho Kim, Chang-Kon Kim, Jong-Wha Chong:
A new architecture of CCK modem based on iterative differential-modulation and phase-detection. 333-336 - Esther Rodríguez-Villegas, Adoración Rueda, Alberto Yúfera:
A 1.5 V 23 MHz low power FGMOS filter. 337-340 - Boris V. Lvov, V. Yu. Petrunkin:
Dynamic behavior of dielectric resonator antennas. 341-344 - Shingo Hatanaka, Kenji Taniguchi:
A ratio-independent algorithmic pipeline analog-to-digital converter. 345-348 - Esdras Juárez-Hernández, Alejandro Díaz-Sánchez:
A novel CMOS charge-pump circuit with positive feedback for PLL applications. 349-352 - Ming Zhang, Nicolas Llaser, Francis Devos:
An optimised design of an improved voltage tripler. 353-356 - Krzysztof Wawryn, Andrzej Mazurek:
Implementation of current mode circuits for programmable neural network. 357-360 - Ming-Dou Ker, Che-Hao Chuang, Wen-Yu Lo:
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. 361-364 - Maria Cristina Piccirilli:
Current conveyor based universal biquad filter. 365-368 - Jens Egerer, Rainer Rodenheber, Michael Reinhold, Hans Hauer:
Fast CMOS current driver for IrDA - applications. 369-372 - Antonio Maffucci, Giovanni Miano:
Associated resistive and discrete circuits in the qualitative analysis of networks of distributed and lumped circuits. 373-376 - Fausto Camboni, Maurizio Valle:
A mixed mode perceptron cell for VLSI neural networks. 377-380 - Phillip K. Wong, Branimir Pejcinovic:
The influence of model parameters on accurate IMD simulations in HBTs. 381-384 - Ey Goo Kang, Seung Hyun Moon, Man Young Sung:
A small sized lateral trench electrode IGBT having improved latch-up and breakdown characteristics for power IC system. 385-388 - Alexander Dollberg, Jürgen Oehm, Ralf Wunderlich, Klaus Schumacher:
Influence of local matching effects on the accuracy of a sequential A/D-converter. 389-392 - Jorge Guilherme, João C. Vital, José E. Franca:
A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction. 393-396 - Gunnar Gudnason, Jannik Hammel Nielsen, Erik Bruun, Morten Haugland:
A distributed transducer system for functional electrical stimulation. 397-400 - G. I. Efremov, N. I. Mukhurov:
High frequency threshold improvement of electro-static micro-relays. 401-404 - Eric Senn, D. Emzivat, Eric Martin:
A smart "single line" pixel sensor for industrial vision. 405-408 - G. Bontempo, Tiziana Signorelli, Francesco Pulvirenti:
Low supply voltage, low quiescent current, ULDO linear regulator. 409-412 - Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin:
A 0.3 V floating-gate differential amplifier input stage with tunable gain. 413-416 - Qing K. Zhu, Tim W. Chan:
Delay/slope budgeting for clock buffer cell design. 417-420 - Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu:
A CMOS low power voltage controlled oscillator with split-path controller. 421-424 - Antonio J. López-Martín, Alfonso Carlosena:
A current-mode CMOS RMS-DC converter for very low-voltage applications. 425-428 - Mokhtar Nibouche, Ahmed Bouridane, Omar Nibouche:
A framework for a wavelet-based high level environment. 429-432 - Pedro G. Fernández, Javier Ramírez, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz:
Implementation of the one dimensional discrete cosine transform using the residue number system. 433-436 - Maja Sliskovic:
Sampling frequency offset estimation and correction in OFDM systems. 437-440 - Mohammed Abo-Zahhad, Bashar A. Rajoub:
ECG compression algorithm based on coding and energy compaction of the wavelet coefficients. 441-444 - A. Das, Uday B. Desai, Priya P. Vaidya:
Design of M-band optimal orthonormal wavelet of compact support for signal de-noising by using the principle of complexity regularization. 445-448 - Mieczyslaw Jessa, Marcin Walentynowicz:
Statistical properties of number sequences generated by 1D chaotic maps considered as a potential source of pseudorandom number sequences. 449-455 - A. Mozsáry, L. Azzinari, K. Król, Veikko Porra:
Theoretical connection between PN-sequences and chaos makes simple FPGA pseudo-chaos sources possible. 457-460 - Giovanna Lombardo, Giuseppe Lullo, Rosalia Zangara:
Experiments on chaotic circuits and crypted data transmission. 461-464 - A. Ingeborg Mahla, Álvaro Torres:
Control of chaotic behavior by parameter commutation methodology. 465-468 - Jer-Min Jou, Yeu-Horng Shiau, Chen-Jen Huang:
An efficient VLSI architecture for HMM-based speech recognition. 469-472 - Haitham S. Cruickshank, Antonio Sánchez-Esguevillas, Zhili Sun, Belén Carro:
Voice over IP over satellite links. 473-476 - Jia-Ching Wang, Jhing-Fa Wang, An-Nan Suen, Yu-Sheng Weng:
A programmable application-specific VLSI architecture for speech recognition. 477-480 - Edward Gatt, Joseph Micallef, Paul Micallef, Edward H. S. Chilton:
Phoneme classification in hardware implemented neural networks. 481-484 - Shu-Min Tsai, Jar-Ferr Yang:
GSM to G.729 speech transcoder. 485-488 - Herman J. Casier:
Requirements for embedded data converters in an ADSL communication system. 489-492 - Koen Uyttenhove, Michiel Steyaert:
Design of high-speed analog-to-digital interface in digital technologies. 493-496 - Jorge Guilherme, Pedro M. Figueiredo, P. Azevedo, G. Minderico, A. Leal, João C. Vital, José E. Franca:
Design considerations for high resolution pipeline ADCs in digital CMOS technology. 497-500 - Rocío del Río, José M. de la Rosa, Fernando Medeiro, Belén Pérez-Verdú, Ángel Rodríguez-Vázquez:
A High-performance sigma-delta ADC for ADSL applications in 0.35 μm CMOS digital technology. 501-504