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ORCIDRenu Mehra
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Journal Articles
- 1997
[j4]Renu Mehra, Lisa M. Guerra, Jan M. Rabaey:
A partitioning scheme for optimizing interconnect power. IEEE J. Solid State Circuits 32(3): 433-443 (1997)- 1996
- [j3]Paul E. Landman, Renu Mehra, Jan M. Rabaey:
An Integrated CAD Environment for Low-Power Design. IEEE Des. Test Comput. 13(2): 72-82 (1996) - [j2]Renu Mehra, Lisa M. Guerra, Jan M. Rabaey:
Low-power architectural synthesis and the impact of exploiting locality. J. VLSI Signal Process. 13(2-3): 239-258 (1996) - 1995
- [j1]Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen:
Optimizing power using transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 12-31 (1995)
Conference and Workshop Papers
- 2015
- [c7]Luca Benini
, Renu Mehra, Mauro Olivieri:
Message from the general chairs. ISLPED 2015: 1-2 - 2012
- [c6]Clive Bittlestone, Jim Kardach, Renu Mehra, David Flynn, Barry M. Pangrle:
Industry focus session on low-power design. ISLPED 2012: 63-64 - [c5]Renu Mehra:
Commercial low-power EDA tools: a review. ISLPED 2012: 67-72 - 2002
- [c4]Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng:
RTL c-based methodology for designing and verifying a multi-threaded processor. DAC 2002: 123-128 - 2000
- [c3]Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch:
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. DATE 2000: 624-631 - 1996
- [c2]Renu Mehra, Jan M. Rabaey:
Exploiting regularity for low-power design. ICCAD 1996: 166-172 - 1995
- [c1]Jan M. Rabaey, Lisa M. Guerra, Renu Mehra:
Design guidance in the power dimension. ICASSP 1995: 2837-2840
Editorship
- 2014
- [e1]Yuan Xie, Tanay Karnik, Muhammad M. Khellah, Renu Mehra:
International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014. ACM 2014, ISBN 978-1-4503-2975-0 [contents]
Coauthor Index
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