default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDATE 2000: Paris, France
- Ivo Bolsens:
2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France. IEEE Computer Society / ACM 2000, ISBN 0-7695-0537-6
Embedded Software Generation
- Rainer Leupers:
Code Selection for Media Processors with SIMD Instructions. 4-8 - Sumit Gupta, Rajesh K. Gupta, Miguel Miranda, Francky Catthoor:
Analysis of High-Level Address Code Transformations for Programmable Processors. 9-13 - Chunghee Kim, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Free MDD-Based Software Optimization Techniques for Embedded Systems. 14-18
Low-Power Issues in System-Level Design
- Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini:
Quantitative Comparison of Power Management Algorithms. 20-26 - Marcello Lajolo, Anand Raghunathan
, Sujit Dey, Luciano Lavagno:
Efficient Power Co-Estimation Techniques for System-on-Chip Design. 27-34 - Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
A Discrete-Time Battery Model for High-Level Power Estimation. 35-39
Circuit Analysis and Synthesis
- Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich:
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. 42-47 - Oscar Guerra, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits. 48-52 - Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte:
Layout-Oriented Synthesis of High Performance Analog Circuits. 53-57 - Sree Ganesan, Ranga Vemuri:
Technology Mapping and Retargeting for Field-Programmable Analog Arrays. 58-64
Embedded Tutorial - Design Practices for Better Reliability and Yield
- Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf:
Tutorial Statement. 66 - Kees Veelenturf:
The Road to Better Reliability and Yield Embedded DfM Tools. 67-68 - Yervant Zorian:
Yield Improvement and Repair Trade-Off for Large Embedded Memories. 69-70 - Chris W. H. Strolenberg:
Stay Away from Minimum Design-Rule Values. 71-72
Embedded Tutorial - System Level Design Using C++
- Diederik Verkest, Joachim Kunkel, Frank Schirrmeister:
System Level Design Using C++. 74-81
IP and Design Reuse
- Roman L. Lysecky, Frank Vahid, Tony Givargis:
Techniques for Reducing Read Latency of Core Bus Wrappers. 84-91 - Frederik Vermeulen, Francky Catthoor, Hugo De Man, Diederik Verkest:
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications. 92-98 - Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli:
Virtual Fault Simulation of Distributed IP-Based Designs. 99-103
Layout
- Xiaoping Tang, D. F. Wong, Ruiqi Tian:
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. 106-111 - Youssef Saab:
A New Effective And Efficient Multi-Level Partitioning Algorithm. 112-116 - Ulrich Brenner, Jens Vygen:
Faster Optimal Single-Row Placement with Fixed Ordering. 117-121 - Youcef Bourai, Chuanjin Richard Shi:
Layout Compaction for Yield Optimization via Critical Area Minimization. 122-125
Heterogeneous Aspects in SOC Testing
- Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu:
Test Synthesis for Mixed-Signal SOC Paths. 128-133 - Makoto Sugihara, Hiroto Yasuura, Hiroshi Date:
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. 134-140 - Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. 141-145 - V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff:
Design and Test Space Exploration of Transport-Triggered Architectures. 146-151
System Specification
- Axel Jantsch, Per Bjuréus:
Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors. 154-160 - Per Bjuréus, Axel Jantsch:
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow. 161-168 - Mark B. Josephs, Dennis P. Furey:
Delay-Insensitive Interface Specification and Synthesis. 169-173
Implementation of Telecom Systems
- Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A 50 Mbit/s Iterative Turbo-Decoder. 176-180 - Uberto Girola, Agostino Picciriello, David Vincenzoni:
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing. 181-185 - Takahiro Murooka, Toshiaki Miyazaki:
Protocol Stack-Based Telecom-Emulator. 186-191
Logic Synthesis: Combination
- Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty:
Transformational Placement and Synthesis. 194-201 - Balakrishna Kumthekar, Fabio Somenzi:
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs. 202-207 - Victor N. Kravets, Karem A. Sakallah:
Constructive Library-Aware Synthesis Using Symmetries. 208-213
BIST for Mixed-Signal Applications
- Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng:
A BIST Scheme for On-Chip ADC and DAC Testing. 216-220 - Yun-Che Wen, Kuen-Jong Lee:
An on Chip ADC Test Structure. 221-225 - Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. 226-230
Decision Diagram Based Methods
- Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang:
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. 232-236 - Praveen Yalagandula, Adnan Aziz, Vigyan Singhal:
Automatic Lighthouse Generation for Directed State Space Search. 237-242 - Jürgen Ruf, Thomas Kropf:
Analyzing Real-Time Systems. 243-248
Multi-Processor Architectures and Design Methods
- Pierre Guerrier, Alain Greiner:
A Generic Architecture for On-Chip Packet-Switched Interconnections. 250-256 - Françoise Harmsze, Adwin H. Timmer, Jef L. van Meerbergen:
Memory Arbitration and Cache Management in Stream-Based Systems. 257-262 - Massimo Baleani, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Claudio Turchetti:
HW/SW Codesign of an Engine Management System. 263-267
Logic Synthesis: Performance Optimization
- Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska:
Wave Steered FSMs. 270-276 - Jovanka Ciric, Gin Yee, Carl Sechen:
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. 277-282 - E. T. A. F. Jacobs, Michel R. C. M. Berkelaar:
Gate Sizing Using a Statistical Delay Model. 283-290
TPG and Diagnosis in BIST
- Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich:
Optimal Hardware Pattern Generation for Functional BIST. 292-297 - Irith Pomeranz, Sudhakar M. Reddy:
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. 298-304 - Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick:
Diagnostic Testing of Embedded Memories Using BIST. 305-309
Architectural-Level Synthesis
- Luc Séméria, Koichi Sato, Giovanni De Micheli:
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C. 312-319 - Satish Ganesan, Ranga Vemuri:
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. 320-325 - Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn:
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. 326-332 - Jörg Henkel, Tony Givargis, Frank Vahid:
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. 333-338
Analysis of Communication Circuits
- Alper Demir, Peter Feldmann:
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits. 340-344 - Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney:
A New Approach for Computation of Timing Jitter in Phase Locked Loops. 345-349 - Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens:
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. 350-354
Logic Synthesis: Covering and PTL Circuits
- Vasco M. Manquinho, João Marques-Silva:
On Using Satisfiability-Based Pruning Techniques in Covering Algorithms. 356-363 - Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo:
An Efficient Heuristic Approach to Solve the Unate Covering Problem. 364-371 - Christoph Scholl, Bernd Becker:
On the Generation of Multiplexer Circuits for Pass Transistor Logic. 372-378
Delay and Functional Testing
- Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva:
On Applying Incremental Satisfiability to Delay Fault Testing. 380-384 - Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti:
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience. 385-389 - Alessandro Fin, Franco Fummi:
A VHDL Error Simulator for Functional Test Generation. 390-395 - Irith Pomeranz, Sudhakar M. Reddy:
Functional Test Generation for Full Scan Circuits. 396-401
Co-Synthesis of Embedded Systems
- Praveen K. Murthy, Shuvra S. Bhattacharyya:
Shared Memory Implementations of Synchronous Dataflow Specifications. 404-410 - Marisa Luisa López-Vallejo, Jesús Grajal, Juan Carlos López:
Constraint-Driven System Partitioning. 411-416 - U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary:
A System-Level Synthesis Algorithm with Guaranteed Solution Quality. 417-424
Hot Topic
- Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis:
How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? 426-433
Wire Performance
- I-Min Liu, Adnan Aziz, D. F. Wong:
Meeting Delay Constraints in DSM by Minimal Repeater Insertion. 436-440 - Kei Hirose, Hiroto Yasuura:
A Bus Delay Reduction Technique Considering Crosstalk. 441-445 - Thorsten Adler, Erich Barke:
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. 446-450 - Matthias Ringe, Thomas Lindenkreuz, Erich Barke:
Static Timing Analysis Taking Crosstalk into Account. 451-455
Analogue Aspects of System Testing
- Uros Kac, Franc Novak, Srecko Macek, Marina Santo Zarnik:
Alternative Test Methods Using IEEE 1149.4. 463-467 - Laurence Goodby, Alex Orailoglu:
Test Quality and Fault Risk in Digital Filter Datapath BIST. 468-475 - Richard Rosing:
A Fault Simulation Methodology for MEMS. 476-483 - Sungju Park, Taehyung Kim:
A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects. 458-462
Abstraction Techniques
- George Logothetis, Klaus Schneider:
Abstraction from Counters: An Application on Real-Time Systems. 486-493 - Felice Balarin:
Automatic Abstraction for Worst-Case Analysis of Discrete Systems. 494-501 - Jae-Young Jang, In-Ho Moon, Gary D. Hachtel:
Iterative Abstraction-Based CTL Model Checking. 502-507
Panel Session - A Design Automation Roadmap for Europe
- Joseph Borel, Frank Ghenassia, Jean-Jacques Bronner, Irmtraud Rugen-Herzig, Wolfgang Rosenstiel, Anton Sauer:
A Design Automation Roadmap for Europe Panel discussion. 510
Interconnect Modelling and Analysis
- Bernard N. Sheehan:
Predicting Coupled Noise in RC Circuits. 517-521 - Youxin Gao, D. F. Wong:
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. 512-516 - Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He:
Clocktree RLC Extraction with Efficient Inductance Modeling. 522-526 - Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee:
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. 527-531
Mixed A/D System Design
- Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas:
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. 534-538 - Michael Scheffler, Gerhard Tröster:
Assessing the Cost Effectiveness of Integrated Passives. 539-543 - Luigi Carro, Adão Antônio de Souza Jr., Marcelo Negreiros, Gabriel Parmegiani Jahn, Denis Teixeira Franco:
Non-Linear Components for Mixed Circuits Analog Front-End. 544-549
Scheduling and Timing Analysis for Real-Time Embedded Systems
- André Hergenhan, Wolfgang Rosenstiel:
Static Timing Analysis of Embedded Software on Advanced Processor Architectures. 552-559 - Iyad Ouaiss, Ranga Vemuri:
Efficient Resource Arbitration in Reconfigurable Computing Environments. 560-566 - Paul Pop, Petru Eles, Zebo Peng:
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis. 567-574
Hot Topic
- Christopher K. Lennard, Patrick Schaumont, Gjalt G. de Jong, Anssi Haverinen, Pete Hardee:
Standards for System-Level Design: Practical Reality or Solution in Search of a Question? 576-583
Dependability Issues in Advanced ICs and Systems
- Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno:
Evaluating System Dependability in a Co-Design Framework. 586-590 - Lorena Anghel, Michael Nicolaidis:
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. 591-598 - Dirk Weiler, Olaf Machul, Dirk Hammerschmidt, Bedrich J. Hosticka:
Detection of Defective Sensor Elements Using Sigma-Delta-Modulation and a Matched Filter. 599-603
High-Level Power Optimization
- Dinesh Ramanathan, Rajesh K. Gupta:
System Level Online Power Management Algorithms. 606-611 - Cheng-Ta Hsieh, Massoud Pedram:
Architectural Power Optimization by Bus Splitting. 612-616 - Tohru Ishihara, Hiroto Yasuura:
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. 617-623 - Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch:
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. 624-631
Panel Session
- Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers:
The Future of Flexible HW Platform Architectures Panel Discussion. 634
Embedded Tutorial
- Sani R. Nassif:
Designing Closer to the Edge. 636-637
Defect Oriented Test
- José T. de Sousa, Vishwani D. Agrawal:
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. 640-644 - Juan M. Díez, Juan Carlos López:
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion. 645-649 - Khaled Saab, Naim Ben-Hamida, Bozena Kaminska:
Parametric Fault Simulation and Test Vector Generation. 650-656
Simulation and Emulation
- Dragos Lungeanu, Chuanjin Richard Shi:
Parallel and Distributed VHDL Simulation. 658-662 - Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi:
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. 663-668 - Stefan Pees, Andreas Hoffmann, Heinrich Meyr:
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. 669-673 - Peter M. Maurer:
Logic Simulation Using Networks of State Machines. 674-678 - Norbert Fröhlich, Volker Gloeckel, Josef Fleischmann:
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level. 679-684
Embedded System Design Frameworks
- Carsten Rust, Friedhelm Stappert, Peter Altenbernd, Jürgen Tacken:
From High-Level Specifications Down to Software Implementations of Parallel Embedded Real-Time Systems. 686-691 - Martyn Edwards, Peter Green:
An Object Oriented Design Method for Reconfigurable Computing Systems. 692-696 - Luigi Carro, Márcio Eduardo Kreutz, Flávio Rech Wagner, Márcio Oyamada:
System Synthesis for Multiprocessor Embedded Applications. 697-702 - Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi:
System Design Based on Single Language and Single-Chip Java ASIP Microcontroller. 703-707
Power and Cost Issues in Testing
- Juin-Ming Lu, Cheng-Wen Wu:
Cost and Benefit Models for Logic and Memory BIST. 710-714 - Nicola Nicolici, Bashir M. Al-Hashimi:
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. 715-722 - Joan Carletta, Christos A. Papachristou, Mehrdad Nourani:
Detecting Undetectable Controller Faults Using Power Analysis. 723-728 - Kabir Gulrajani, Michael S. Hsiao:
Multi-Node Static Logic Implications for Redundancy Identification. 729-733
Poster Papers
- Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli:
Dynamic Power Management of Laptop Hard Disk. 736 - Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel:
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints. 737 - Christian Paulus, Ulrich Kleine, Roland Thewes:
Area Optimization of Analog Circuits Considering Matching Constraints. 738 - F. M. Pérez-Montes, Fernando Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool. 739 - Ulf Pillkahn:
Evaluation of Interconnects with TDR. 740 - Peter Bach, Michael Bosch:
Structural Testing on Real Boards. 741 - Lovic Gauthier, Ahmed Amine Jerraya:
Cycle-True Simulation of the ST10 Microcontroller. 742 - Adam Morawiec, Raimund Ubar, Jaan Raik:
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. 743 - José Machado da Silva, J. Soeiro Duarte, José Silva Matos:
Mixed-Signal BIST Using Correlation and Reconfigurable Hardware. 744 - Karem A. Sakallah, Fadi A. Aloul, João P. Marques Silva:
An Experimental Study of Satisfiability Search Heuristics. 745 - Sunho Chang, Jong-Sun Kim, Lee-Sup Kim:
A Memory Architecture with 4-Address Configurations for Video Signal Processing. 746 - Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel:
A Hardware Platform for VLIW Based Emulation of Digital Designs. 747 - Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Architecture Exploration of Parameterizable EPIC SOC Architectures. 748 - Sriram Govindarajan, Ranga Vemuri:
Improving the Schedule Quality of Static-List Time-Constrained Scheduling. 749 - Congguang Yang, Maciej J. Ciesielski:
Synthesis for Mixed CMOS/PTl Logic. 750 - Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio:
TOP: An Algorithm for Three-Level Optimization of PLDs. 751 - Janusz Sosnowski, Tomasz Bech:
Testing Arithmetic Coprocessor in System Environment. 752 - José Manuel Moya, Francisco Moya, Juan Carlos López, Santiago Domínguez:
A Flexible Specification Framework for Hardware-Software Codesign. 753 - Jingyan Zuo, Stephen W. Director:
An Integrated Design Environment for Early Stage Conceptual Design. 754 - Hilary J. Kahn, Andy Carpenter, Nigel A. Whitaker:
A Web-Based System for Assessing and Searching for Designs. 755 - Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos:
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. 756 - Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian:
Effective Low Power BIST for Datapaths. 757 - Dirk W. Hoffmann, Thomas Kropf:
Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits. 758 - Jens Schönherr, Bernd Straube:
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level. 759 - Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, Javier Sosa:
A Single Phase Latch for High Speed GaAs Domino Circuits. 760 - Alex Niemegeers, Gjalt G. de Jong:
An Incremental Specification Flow for Real Time Embedded Systems. 761 - Valery A. Vardanian, Liana B. Mirzoyan:
Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check. 762 - Cecilia Metra, Michele Favalli, Bruno Riccò:
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. 763 - Carsten Wegener, Michael Peter Kennedy:
Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs. 765
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-23 00:30 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
