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Chih-Sheng Hou

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Journal Articles

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2015
[j6]
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Chih-Sheng Hou, Jin-Fu Li:
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1720-1728 (2015)
2014
[j5]
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Chih-Sheng Hou, Jin-Fu Li:
Testing Disturbance Faults in Various NAND Flash Memories. J. Electron. Test. 30(6): 643-652 (2014)
[j4]
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Chih-Sheng Hou, Jin-Fu Li, Ting-Jun Fu:
A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2020-2024 (2014)
2011
[j3]
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Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng:
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1731-1743 (2011)
2010
[j2]
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Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou:
A Built-in Method to Repair SoC RAMs in Parallel. IEEE Des. Test Comput. 27(6): 46-57 (2010)
[j1]
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Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou:
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1361-1366 (2010)

Conference and Workshop Papers

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2016
[c9]
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Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC 2016: 1-7
2014
[c8]
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Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo:
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS 2014: 143-148
2013
[c7]
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Chih-Sheng Hou, Jin-Fu Li:
Testing Disturbance Faults in Various NAND Flash Memories. Asian Test Symposium 2013: 221-226
[c6]
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Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4
[c5]
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Chih-Sheng Hou, Jin-Fu Li:
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs. VTS 2013: 1-6
[c4]
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Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6
2012
[c3]
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Chih-Sheng Hou, Jin-Fu Li:
Disturbance fault testing on various NAND flash memories. ETS 2012: 1
2010
[c2]
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  - conf/delta/HouLC10
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Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou:
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. DELTA 2010: 3-7
[c1]
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Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li:
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. VTS 2010: 21-26

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