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Tsung-Yi Tsai
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2020 – today
- 2021
- [j9]Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee:
2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. Circuits Syst. Signal Process. 40(6): 2824-2840 (2021) - [j8]Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, I-Yu Huang, Yu-Cheng Lin, Tzung-Je Lee, Guan-Ru Chen:
High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors. Circuits Syst. Signal Process. 40(9): 4187-4195 (2021)
2010 – 2019
- 2019
- [j7]Chua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee:
500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations. Circuits Syst. Signal Process. 38(2): 556-568 (2019) - [j6]Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang:
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 116-120 (2019) - [j5]Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih:
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2464-2468 (2019) - [c8]Chun-Ting Chen, Tsung-Yi Tsai, Yi-Jen Chiu, Chua-Chin Wang:
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems. ASICON 2019: 1-4 - [c7]Tsung-Yi Tsai, Ting-Sheng Wang, Yi-Jen Chiu, Chua-Chin Wang:
A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs. ICICDT 2019: 1-4 - 2017
- [j4]Je-Wei Lan, Chia-Hsu Hsieh, I-Yu Huang, Yu-Cheng Lin, Tsung-Yi Tsai, Chua-Chin Wang:
Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine. Sensors 17(12): 2760 (2017) - [j3]Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang:
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3166-3174 (2017) - [c6]Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang:
A pipeline ROM-less DDFS using equal-division interpolation. ISOCC 2017: 19-20 - 2016
- [c5]Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang:
A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above. ICICDT 2016: 1-4 - [c4]Tsung-Yi Tsai, Yu-Lin Teng, Chua-Chin Wang:
A nano-scale 2×VDD I/O buffer with encoded PV compensation technique. ISCAS 2016: 598-601 - 2015
- [j2]Chua-Chin Wang, Tsung-Yi Tsai, Wen-Je Lu, Chih-Lin Chen, Yi-Lun Wu:
A 30 V rail-to-rail operational amplifier. Microelectron. J. 46(10): 911-915 (2015) - [j1]Chua-Chin Wang, Wen-Je Lu, Tsung-Yi Tsai:
Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 217-221 (2015) - [c3]Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin:
A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology. ICICDT 2015: 1-4 - 2013
- [c2]Hui-Yuan Liu, Tsung-Yi Tsai, Tai-Kuei Ren:
An innovative application by incorporating RFID technology with current available glucometer. iCAST/UMEDIA 2013: 558-563
2000 – 2009
- 2008
- [c1]Chung-Ming Huang, Chao-Hsien Lee, Jun-Hao Zhuang, Tsung-Yi Tsai, Chi-Chang Liu:
SIP-Based Cross-Domain Proxy Handoff for Mobile Streaming Services. ISPAN 2008: 4-9
Coauthor Index
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