- Bipul C. Paul, Krishnendu Chakrabarty:
Advances in nanoelectronics circuits and systems [Editorial]. IET Comput. Digit. Tech. 3(6): 551-552 (2009) - Jonathan Phillips, Arvind Sudarsanam, Harikrishna Samala, Ramachandra Kallam, J. Carver, Aravind Dasu:
Methodology to derive context adaptable architectures for FPGAs. IET Comput. Digit. Tech. 3(1): 124-141 (2009) - Irith Pomeranz, Sudhakar M. Reddy:
Definition and generation of partially-functional broadside tests. IET Comput. Digit. Tech. 3(1): 1-13 (2009) - Irith Pomeranz, Sudhakar M. Reddy:
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. IET Comput. Digit. Tech. 3(1): 85-93 (2009) - Irith Pomeranz, Sudhakar M. Reddy:
Test vector chains for increasing the fault coverage and numbers of detections. IET Comput. Digit. Tech. 3(2): 222-233 (2009) - Irith Pomeranz, Sudhakar M. Reddy:
Test compaction methods for transition faults under transparent-scan. IET Comput. Digit. Tech. 3(4): 315-328 (2009) - Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
, Aleksandar Ignjatovic:
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Comput. Digit. Tech. 3(1): 94-108 (2009) - Jaan Raik
, Vineeth Govind, Raimund Ubar
:
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Comput. Digit. Tech. 3(5): 476-486 (2009) - Jacqueline E. Rice, Kenneth B. Kent
:
Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems. IET Comput. Digit. Tech. 3(3): 247-258 (2009) - Samuel Rodrigo, Simone Medardoni, José Flich
, Davide Bertozzi, José Duato
:
Efficient implementation of distributed routing algorithms for NoCs. IET Comput. Digit. Tech. 3(5): 460-475 (2009) - Frank Rogin, Thomas Klotz, Görschwin Fey
, Rolf Drechsler
, Steffen Rülke:
Advanced verification by automatic property generation. IET Comput. Digit. Tech. 3(4): 338-353 (2009) - Erno Salminen, Cristian Grecu, Timo D. Hämäläinen, André Ivanov:
Application modelling and hardware description for network-on-chip benchmarking. IET Comput. Digit. Tech. 3(5): 539-550 (2009) - Benjamin Carrión Schäfer
, Taewhan Kim:
Autonomous temperature control technique in VLSI circuits through logic replication. IET Comput. Digit. Tech. 3(1): 62-71 (2009) - Ozgur Sinanoglu
, Mohammed Al-Mulla, Mohammed Nael Taha:
Utilisation of inverse compatibility for test cost reductions. IET Comput. Digit. Tech. 3(2): 195-204 (2009) - Rastislav J. R. Struharik, Ladislav A. Novak:
Intellectual property core implementation of decision trees. IET Comput. Digit. Tech. 3(3): 259-269 (2009) - George Theodoridis, Nikolaos Vassiliadis, Spiridon Nikolaidis
:
An integer linear programming model for mapping applications on hybrid systems. IET Comput. Digit. Tech. 3(1): 33-42 (2009) - Xuan-Tu Tran
, Yvain Thonnart
, Jean Durupt, Vincent Beroulle, Chantal Robach:
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. IET Comput. Digit. Tech. 3(5): 487-500 (2009) - Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. 3(6): 581-592 (2009) - F.-M. Wang, W.-C. Wang, James Chien-Mo Li:
Time-space test response compaction and diagnosis based on BCH codes. IET Comput. Digit. Tech. 3(3): 304-313 (2009) - Yi-Hsin Wu, Cheng-Juei Yu, Sheng-De Wang:
Heuristic algorithm for the resource constrained scheduling problem during high-level synthesis. IET Comput. Digit. Tech. 3(1): 43-51 (2009) - Shan Yan, Bill Lin:
Joint multicast routing and network design optimisation for networks-on-chip. IET Comput. Digit. Tech. 3(5): 443-459 (2009) - Qiaoyan Yu, Paul Ampadu:
Adaptive error control for nanometer scale network-on-chip links. IET Comput. Digit. Tech. 3(6): 643-659 (2009)