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Publication search results
found 167 matches
- 2024
- Lorenzo Sonnino, Shaswot Shresthamali, Yuan He, Masaaki Kondo:
DAISM: Digital Approximate In-SRAM Multiplier-Based Accelerator for DNN Training and Inference. DATE 2024: 1-6 - Gaoming Du, Zhuo Chen, Zhenmin Li, Xiaolei Wang, Duoli Zhang:
A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital Signature. ACM Great Lakes Symposium on VLSI 2024: 258-262 - Yasir Ali Shah, Ciara Rafferty, Ayesha Khalid, Safiullah Khan, Khalid Javeed, Máire O'Neill:
Efficient Soft Core Multiplier for Post Quantum Digital Signatures. ISCAS 2024: 1-5 - 2023
- Perumal Mahendran, M. S. Kavitha, R. Radhika, C. Kotteeswaran:
Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application. Concurr. Comput. Pract. Exp. 35(6): 1 (2023) - K. Saritha Raj, P. Rajesh Kumar, M. Satyanarayana:
Capricious Digital Filter Design and Implementation Using Baugh-Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application. Circuits Syst. Signal Process. 42(11): 6726-6748 (2023) - Shengqi Yu, Fei Xia, Rishad A. Shafik, Domenico Balsamo, Alex Yakovlev:
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption. Integr. 93: 102045 (2023) - Hongyang Hu, Xiwei Wang, Zi Wang, Haiyang Zhou, Danian Dong, Jinshan Yue, Wan Pang, Xiaoxin Xu, Chunmeng Dou:
A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2044-2052 (2023) - Amitesh Sridharan, Fan Zhang, Yang Sui, Bo Yuan, Deliang Fan:
DSPIMM: A Fully Digital SParse In-Memory Matrix Vector Multiplier for Communication Applications. DAC 2023: 1-6 - Mohit Gupta, Stefan Cosemans, Peter Debacker, Wim Dehaene:
A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. ESSCIRC 2023: 417-420 - Denis Flores, Dominique Dallet, Andrei Vladimirescu, Andreia Cathelin, Yann Deval:
High-Resolution Fractional Digital Frequency Divider using a Binary-Rate Multiplier. NEWCAS 2023: 1-5 - Lorenzo Sonnino, Shaswot Shresthamali, Yuan He, Masaaki Kondo:
DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference. CoRR abs/2305.07376 (2023) - 2022
- Srikanth Immareddy, Arunmetha Sundaramoorthy:
A survey paper on design and implementation of multipliers for digital system applications. Artif. Intell. Rev. 55(6): 4575-4603 (2022) - Ahmad Ghiasi, Abdulhamid Zahedi:
Field-programmable gate arrays-based Morris-Lecar implementation using multiplierless digital approach and new divider-exponential modules. Comput. Electr. Eng. 99: 107771 (2022) - Nagarajan Shanmugam, Vijeyakumar Krishnasamy Natarajan, Kalaiselvi Sundaram, Natarajan Saravanakumar:
Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing. Comput. Syst. Sci. Eng. 42(2): 619-638 (2022) - Sudhanshu Janwadkar, Rasika Dhavse:
Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures. J. Circuits Syst. Comput. 31(13): 2250239:1-2250239:34 (2022) - Guodao Zhang, Ruyu Liu, Yisu Ge, Abdulilah Mohammad Mayet, Sixian Chan, Guoqing Li, Ehsan Nazemi:
Investigation on the Wilson Neuronal Model: Optimized Approximation and Digital Multiplierless Implementation. IEEE Trans. Biomed. Circuits Syst. 16(6): 1181-1190 (2022) - Jianming Cai, Han Bao, Mo Chen, Quan Xu, Bocheng Bao:
Analog/Digital Multiplierless Implementations for Nullcline-Characteristics-Based Piecewise Linear Hindmarsh-Rose Neuron Model. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2916-2927 (2022) - Rongjin Xu, Dawei Ye, Chuanjin Richard Shi:
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2832-2844 (2022) - K. Gavaskar, D. Malathi, G. Ravivarma, V. Krithika Devi, M. Megala, S. Megaraj Begam:
A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors. Wirel. Pers. Commun. 124(2): 1297-1315 (2022) - Hongyang Hu, Zi Wang, Xiaoxin Xu, Kai Xi, Kun Zhang, Junyu Zhang, Chunmeng Dou:
A 55nm 32Mb Digital Flash CIM Using Compressed LUT Multiplier and Low Power WL Voltage Trimming Scheme for AI Edge Inference. APCCAS 2022: 1-5 - Chaeyoung Jang, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim:
A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC. ICEIC 2022: 1-2 - Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi:
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. ISSCC 2022: 1-3 - Rongjin Xu, Dawei Ye, Sirou Li, Chuanjin Richard Shi:
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. ISSCC 2022: 214-216 - 2021
- Muhammad Riaz ur Rehman, Arash Hejazi, Imran Ali, Muhammad Asif, SeongJin Oh, Pervesh Kumar, YoungGun Pu, Sang-Sun Yoo, Keum-Cheol Hwang, Youngoo Yang, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, Kang-Yoon Lee:
An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking. IEEE Access 9: 152984-152992 (2021) - Kalaiselvi Sundaram, Vijeyakumar Krishnasamy Natarajan, Nagarajan Shanmugam, Kousalya Manoharan, Ramya Ramasamy, Sriram Kumar:
Area-Energy-Error Optimized Faithful Multiplier for Digital Signal Processing. Circuits Syst. Signal Process. 40(12): 6224-6241 (2021) - Jialin Xu, Yan Li, Xiaobin Hong, Jifang Qiu, Yong Zuo, Wei Li, Hongxiang Guo, Jian Wu:
Multiplier-Free Parallel Fixed-Point Adaptive Equalizer for Real-Time Digital Coherent Communication. IEEE Commun. Lett. 25(7): 2380-2384 (2021) - Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong:
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021) - Adriana N. Borodzhieva, Ivanka D. Tsvetkova, Snezhinka Zaharieva, Dimitar Dimitrov, Valentin Mutkov:
Project-Based Learning Approach Applied in the Course "Digital Electronics" for Studying the Topic "Binary Multipliers". CompSysTech 2021: 212-217 - En-Hui Zhang, Shih-Hsu Huang:
Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing. ICCE 2021: 1-5 - 2020
- Hajar Asgari, Babak Mazloom-Nezhad Maybodi, Raphaela Kreiser, Yulia Sandamirskaya:
Digital Multiplier-Less Spiking Neural Network Architecture of Reinforcement Learning in a Context-Dependent Task. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(4): 498-511 (2020)
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