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ORCIDAPCCAS 2022: Shenzhen, China
- IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022. IEEE 2021, ISBN 978-1-6654-5073-7
- Ronghao Zhang, Xu Liu, Zhijie Chen, Peiyuan Wan, Tao Chen:
A Neural Recording IC Design with on-chip CMOS Electrode Array for Brain-machine Interface. 1-5 - Changlong Lv, Liyu Lin, Honghui Deng, Junhui Wang, Yun Chen:
A Low-latency Multi-format Carrier Phase Recovery Hardware for Coherent Optical Communication. 1-4 - Xinwei Yu, Fan Ye, Junyan Ren:
A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound Transducers. 1-4 - Chien-Cheng Tseng, Su-Ling Lee:
An Eigen-decomposition Free Method for Computing Graph Fourier Transform Centrality. 1-6 - Feifei Chen, Ka-Fai Un, Wei-Han Yu
, Pui-In Mak, Rui Paulo Martins:
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting. 1-5 - Aniruddha Roy, Preetham N. Reddy, Nitin Agarwal, Nikhil Das:
Achieving < 1% Precision Clocking Solution with External-R under Practical Constraints. 1-5 - Dingbang Liu, Wei Mao, Haoxiang Zhou, Jun Liu, Qiuping Wu, Haiqiao Hong, Hao Yu:
An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout. 1-5 - Leyi Chen, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Cong Shi, Min Tian:
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. 1-5 - Hao Wang, Jianyang Yan:
FPGA Implementation of Matrix Decomposition Based FIR Filter. 1-4 - Zhihuai Zhang, Weiqian Zhang, Shisheng Xiong, Yudi Zhao:
An Accurate and Time-Efficient Subtractor by Cross Format Coding in Stochastic Computing. 1-5 - Ruike Chen, Yaowei Ma, Yao Wang:
A 40.6 ppm/°C 368 nW 10 kHz Relaxation Oscillator with Temperature-Sensor-based Piece-Wise Compensation Technique. 1-5 - Rajat Kumar, Divyanshu Divyanshu, Danial Khan, Selma Amara, Yehia Massoud:
Modeling of Sneaky Hardware Trojan Using Spin-orbit Torque Assisted Magnetic Tunnel Junction for High Speed Digital Circuits. 1-5 - Yuxin Lin, Wenye Liu, Chip-Hong Chang:
Deep Texture-Depth-Based Attention for Face Recognition on IoT Devices. 1-5 - Jipeng Ge, Chenggang Yan, Xuan Zhao, Ke Chen, Bi Wu, Weiqiang Liu:
An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications. 1-5 - Dong Suk Kang, Shimeng Yu:
Design-Technology Co-optimization for Cryogenic Tensor Processing Unit. 1-4 - Yubin Wang, Karnika Biswas, Liwen Zhang, Hakim Ghazzai, Yehia Massoud:
3D Autonomous Navigation of UAVs: An Energy-Efficient and Collision-Free Deep Reinforcement Learning Approach. 1-5 - Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang:
High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber. 1-5 - Xiao Han, Xiyuan Tang, Yanxing Suo, Qiao Cai, Xinzi Xu, Tianwei Wan, Yang Zhao:
A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC. 1-5 - Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang:
A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. 1-5 - Yajun Lin, Haozheng Wan, Jianxin Yang, Ka Nang Leung:
An Ultra-Low-Supply Output-Capacitorless LDO with Signal- and Transient-Enhancement. 1-5 - Shuo Feng, Fuzhan Chen, Zhenghao Li, Wentao Zhou, Dongfan Xu, Chun-Zhang Chen, Xuhui Liu, Hanming Wu, Quan Pan:
A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS. 1-5 - Hongyang Hu, Zi Wang, Xiaoxin Xu, Kai Xi, Kun Zhang, Junyu Zhang, Chunmeng Dou:
A 55nm 32Mb Digital Flash CIM Using Compressed LUT Multiplier and Low Power WL Voltage Trimming Scheme for AI Edge Inference. 1-5 - Tianxian Wu, Yuting Zhang, Yanhan Zeng:
A 0.3-μA Quiescent Current Output Capacitor-Less LDO with Dynamic Slew Rate Enhance Buffer. 1-5 - Chenyu Xie, Chunmei Yang, Hailong Jiao:
A Karnaugh Map Approximate Adder With Intrinsic Error Compensation. 10-14 - Liao-Chuan Chen, Zhaofang Li, Yi-Jhen Lin, Kuan-Pei Lee, Kea-Tiong Tang:
A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization. 15-19 - Xundong Gong, Yifan Zuo, Yu Zhang, Ming Chen, Haicheng Tu:
Key Features Selection of Power System Operation Via Improved Clustering Algorithm. 25-29 - Hao-Wen Kuo, Rui-Hsuan Wang, Zhaofang Li, Shih-Ting Lin, Meng-Fan Chang, Kea-Tiong Tang:
A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory Architecture. 30-34 - Shaobo Luo, Zhiyuan Xie, Gengxin Chen, Lei Cui, Mei Yan, Xiwei Huang, Shuwei Li, Changhai Man, Wei Mao, Hao Yu:
Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA Sequencing. 35-40 - Ping-Li Huang, Chen-Han Hsu, Yu-Hsiang Cheng, Zhaofang Li, Yu-Hsuan Lin, Kea-Tiong Tang:
A 104.76-TOPS/W, Spike-Based Convolutional Neural Network Accelerator with Reduced On-Chip Memory Data Flow and Operation Unit Skipping. 41-45 - Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu:
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. 46-49 - Aymen Hamrouni, Hakim Ghazzai, Yehia Massoud:
Multi-modal Asymmetric Autoencoders for Massive Photo Collection Applications. 50-54 - Ming Liu, Yifan He, Hailong Jiao:
An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator. 55-59 - Woobean Lee, Pangi Park, SeongHwan Cho:
Reduction of Motion Artifact in PPG signal with CDS-LMS Filter. 60-64 - Feng Xia, Zhaoyang Zhang, Jie Yang, Mohamad Sawan:
Compact Power Front-end Management for Wireless Supply of Multi-voltages to Neuromodulators. 65-68 - Jinbo Chen, Hui Wu, Jie Yang, Mohamad Sawan:
A 97 fJ/Conversion Neuron-ADC with Reconfigurable Sampling and Static Power Reduction. 73-76 - Qiang Wang, Anning Liu, Songping Mai:
A 6.78 MHz High-Efficiency Wireless Power Transfer Transmitter With Adaptive Dead-Time Control and Transistor-Width Switching for Implantable Medical Devices. 77-81 - Yi Mao, Yuyang Du, Yongjun He, Gengzhen Qi, Pui-In Mak:
A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor Technique. 82-85 - Shiying Zhang, Xian Tang:
Nanowatt High Order Analog Fully-Differential Bandpass Filter with Passive Switched-Capacitor Circuits. 86-90 - Ruolin Zhou, Heng Liu, Wending Qi, Xian Tang, Songping Mai:
A Fast-Transient Response Capacitor-Less FVF-LDO in 22-nm CMOS Technology. 91-94 - Jitumani Sarma, Rakesh Biswas:
A Power-Aware ECG Transmission Framework with Server Aided Lossless Compression. 95-99 - Yunhao Ma, Xiwei Fang, Pingcheng Dong, Xinyu Guan, Ke Li, Lei Chen, Fengwei An:
Subpixel Interpolation Disparity Refinement for Semi-Global Matching. 105-109 - Mohamed Karaa, Hakim Ghazzai, Lokman Sboui, Hichem Besbes, Yehia Massoud:
Unsupervised Image Dataset Annotation Framework for Snow Covered Road Networks. 110-114 - Zhoudeng Li, Xian Tang:
A 30.6-41.5uW 10-bit Column Parallel Single-Slope ADC with Minimum Voltage Feedback for CMOS Image Sensors. 115-118 - Yichen Ouyang, Xianglong Wang, Gang Shi, Lei Chen, Fengwei An:
A Dynamic JPEG CODEC with Adaptive Quantization Table for Frame Storage Compression. 119-122 - Juzhe Li, Xu Liu, Peiyuan Wan, Zhijie Chen:
A 4-Channel Neural Stimulation IC Design with Charge Balancing and Exponential Current Output. 123-127 - Weisong Liang, Xu Liu, Weijian Chen, Zeyu Lu, Peiyuan Wan, Zhijie Chen:
A Wireless Power Design with High PCE and Fast Transient Response over a Large Loading Range for Multi-channel Neural Stimulators. 128-133 - Wending Qi, Anning Liu, Ruolin Zhou, Songping Mai:
Design and Optimization of Inductive Coils for 2FSK-based Power and Data Transmission for Biomedical Implants. 134-138 - Weijian Chen, Xu Liu, Weisong Liang, Zeyu Lu, Peiyuan Wan, Zhijie Chen:
A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine Interface. 144-148 - Junsheng Chen, Lingxin Meng, Menglian Zhao, Zhichao Tan:
An Energy-Efficient Readout Circuit Based on Incremental Delta-Sigma ADC with Decimation Filter for CMOS Image Sensors. 149-152 - Yu Lei, Qishen Fang, Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
High Linearity BJT-Based Time-Domain CMOS Temperature Sensor. 153-156 - Peng Zhang, Xiaoyong He, Shuhao Lai, Zehui Wu:
A Third-Order CIFF Noise-Shaping SAR ADC with Nonbinary Split-Capacitor DAC. 162-165 - Ko-Chi Kuo, Ying-Ju Sung:
A 12-bit 1 GS/s Current Steering DAC with the Appointed and Thermometer Coding Scheme. 171-175 - Jinge Ma, Yanjin Lyu, Yuanqi Hu:
A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage Amplification. 176-180 - Zhanpeng Yang, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen:
An 8-b 8-GS/s Time-Interleaved SAR ADC With Foreground Offset Calibration in 28nm CMOS. 181-184 - Eric J. Wyers:
Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization. 185-189 - Zekun Zhou, Zhijian Zhang, Lichen Peng:
Design of a High Voltage Level Shift with High dV/dt Immunity and High Speed. 190-194 - Daiki Ogata, Ryosuke Kamiya, Yusuke Toyoshima, Kenichi Ohhata:
A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging. 195-198 - Jinge Ma, Yuanqi Hu:
Analysis and Design of High-Speed and Low-Distortion Bootstrapped Switches. 199-203 - Yutong Zhao, Fan Ye, Junyan Ren:
A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC. 209-212 - Minghao Jiang, Chenyang Han, Weibo Li, Jiangfeng Wu, Yongzhen Chen:
0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop Biases. 213-216 - Srikrishna Vasudev, Kartickraj K, Anuj Grover:
Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM. 222-225 - Laimin Du, Leibin Ni, Xiong Liu, Wei Mao, Hao Yu:
A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation. 226-230 - Zhikun He, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen:
Low Power and High Speed Designs of CIC Filter for Sigma-Delta ADCs. 236-240 - Sae Goto, Minoru Watanabe, Nobuya Watanabe:
Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration. 241-245 - Xudong Wang, Geng Li, Jiacong Sun, Huanjie Fan, Yong Chen, Hailong Jiao:
Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks. 246-250 - Jyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang:
A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. 251-255 - Yuqiang Cui, Weiwei Shan:
A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOS. 256-259 - Chaolin Rao, Haochuan Wan, Yueyang Zheng, Pingqiang Zhou, Xin Lou:
An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field Accelerator. 260-264 - Xuan Zhao, Chenggang Yan, Chenghua Wang, Weiqiang Liu:
Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm. 265-269 - Haochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou:
SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network. 270-274 - Chunbiao Pan, Yidie Ye, Huakang Xia:
High Precision Hysteresis Controlled MPPT Circuit for Vibration Energy Harvesting. 280-283 - Xuliang Wang, Wing-Hung Ki, Philip K. T. Mok:
A 65-nm Clock-Domain-Crossing Controller for Digital LDO Regulator with 1.7-ns Response Time. 284-288 - Yue Shi, Zhou Gong, Jiawen Wang, Zekun Zhou, Bo Zhang:
A 3-D Maximum Power Point Tracking Technique for Energy Harvesting System Based on Hill-Climbing Algorithm. 294-298 - Imran Pervez, Charalampos Antoniadis, Hakim Ghazzai, Yehia Massoud:
A Centralized Multi-String PV System Control with Multi-Dimensional MPPT Control. 304-308 - Quyet Nguyen, Huy-Dung Han, Loan Pham-Nguyen, Hanh-Phuc Le:
A 60V Input Integrated 3-to-1 Dual Inductor Hybrid Dickson Converter. 309-313 - Mengli Zou, Xinzi Xu, Qiao Cai, Yanxing Suo, Tianwei Wan, Jian Zhao, Yang Zhao:
Store, Supply, Extract and Recycle: A Boost/Buck Reconfigurable Converter for Thermal Energy Harvesting. 314-318 - Huihua Li, Qiaobo Ma, Xuchu Mu, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
Adaptive Line-Transient Enhancement Techniques for Dual-Path Hybrid Converter Achieving Ultra-Low Output Overshoot/Undershoot. 319-323 - Benqing Guo, Xingyue Liao, Yao Wang:
A 22 mW CMOS Receiver Frontend Using Active-Feedback Baseband and Passive-Voltage Mixers Embedded in Current Mirrors. 324-328 - Leiming Wang, Xiongshi Luo, Dongfan Xu, Zhang Qiu, Yiyang Yan, Quan Pan:
A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS. 333-336 - Wenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, Shunli Ma:
A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process. 337-340 - Liyu Lin, Junhui Wang, Xiaoyang Zeng, Yun Chen:
An Approximate-Computing-Based Adaptive Equalizer for Polarization Mode Dispersion. 346-349 - Xinyuan Qiao, Keyue Deng, Yuxing Chen, Suwen Song, Zhongfeng Wang:
Low-Complexity Parallel Syndrome Computation for BCH Decoders Based on Cyclotomic FFT. 350-354 - Shan Gao, Zhi-Jian Chen, Xiangfeng Sun, Siyuan Yang, Bin Li, Xiao-Ling Lin:
A Reconfigurable Active-RC Filter with Variable Gain and An RC-Reused Tuning Circuit. 355-359 - Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, Nan Qi:
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. 360-363 - Tuy Tan Nguyen, Hanho Lee:
Toward A Real-Time Elliptic Curve Cryptography-Based Facial Security System. 364-367 - Min Hu, Pengxing Yi, Biting Lei, Wentao Lin:
Time Skew Calibration for Time-Interleaved Analog-to-Digital Converters. 378-382 - Chien-Cheng Tseng, Su-Ling Lee:
Design of Matrix Filter Using Discrete Cosine Transform and Path Graph. 383-388 - Qinyuan Zhang, Suwen Song, Zhongfeng Wang:
Low-Complexity Dynamic Single-Minimum Min-Sum Algorithm and Hardware Implementation for LDPC Codes. 389-393 - Chenyang Shi, Jing Jin, Boyi Wei, Yuzhen Li, Wenzhuo Li, Hanxiao Liu, Yibo Zhang, Shaobo Luo:
A High-speed Event-based Object Tracking with Heterogeneous Computing Hardware. 394-399 - Kai Sun, Jihong Zhu, Jie Liang:
Emotion Recognition of Physical Activities for Health Monitoring Using Machine Learning. 400-403 - Karnika Biswas, Hakim Ghazzai, Indrani Kar, Yehia Massoud:
Optimal Evasive Path Planning with Velocity Constraint. 409-413 - Yuzhong Jiao, Yiu Kei Li, Chi-Hong Chan, Yun Li, Zhilin Ai:
Thermometer Code of Log Mel-Frequency Spectral Coefficient for BNN-based Keyword Spotting System. 414-418 - Xundong Gong, Jinyue Lu, Shaolei Zong, Ming Chen, Yongxiang Xia:
Fast Responsive Framework for Optimal Power Flow Analysis in Power System. 419-423 - Onur Karatas, Kaya Demir, Salih Ergün:
Chaotic Sampling of Double Scroll Chaos for Digital Random Number Generation. 424-427 - Xundong Gong, Shibo Liao, Fei Hu, Xiaoqing Hu, Chunshan Liu:
Autoencoder-Based Anomaly Detection for Time Series Data in Complex Systems. 428-433 - Xundong Gong, Jia Ma, Ming Chen, Shaolei Zong, Chunshan Liu:
Change Point Detection for Time Series Data in Complex Systems. 434-438 - Gulafshan Gulafshan, Rajat Kumar, Danial Khan, Selma Amara, Yehia Massoud:
Bitwise Logical Operations in VCMA-MRAM. 439-443 - Yiyang Zhang, Tianyi Wang, Jun Lan, Wenhui Wang, Longyang Lin, Yida Li:
Quantum Efficiency Enhancement in Si Avalanche Photodiodes in the NIR Regime via Surface Texturing Towards Autonomous Driving Applications. 444-448 - Jinxuan Liang, Zhuoxuan Zhu, Yida Dong, Lei Lei, Yida Li, Mei Shen, X.-D. Xiang:
Simulation of Gap Structure Optical Waveguide with Phase Change Materials. 454-457 - Divyanshu Divyanshu, Rajat Kumar, Danial Khan, Selma Amara, Yehia Massoud:
Logic Locking for Hardware Security Using Voltage-Gated Spin-orbit Torque Magnetic Tunnel Junction. 458-462 - Zhixiang Liu, Shiyou Wei, Gengzhen Qi, Pui-In Mak:
A 32dBm OOB-IIP3 BW-Extended 5G-NR Receiver with 4th-Order Gain-Boosted N-Path LNA. 463-467 - Surajit Kumar Nath, Daekeun Yoon:
A 300-GHz Wideband Injection Locked Frequency Quadrupler in 250-nm InP DHBT Technology. 468-471 - Chunhong Chen, Suoyue Zhan:
A Hybrid Method for Signal Probability Estimation with Combinational Circuits. 472-475 - Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha:
Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs. 476-480 - Shaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng:
An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits. 481-484 - Hua Fan, Kaicong Dong, Xiuhua Xie, Quanyuan Feng, Qiang Hu:
"Fusion, Interaction, and Training": Cultivating Innovative Leading Talents. 485-488 - Aleksandr Kornilov:
Implementation of a Training Computer Program for Circuit Analysis in the Time Domain. 489-492 - Xi Chen, An Guo, Xinbing Xu, Xin Si, Jun Yang:
A Quantization Model Based on a Floating-point Computing-in-Memory Architecture. 493-496 - Linfang Wang, Junjie An, Wang Ye, Weizeng Li, Hanghang Gao, Yangu He, Jianfeng Gao, Jinshan Yue, Lingyan Fan, Chunmeng Dou:
RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference. 497-500 - Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang:
A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators. 501-504 - Liang Chang, Pan Zhao, Jun Zhou:
Pipelined Computing-in-Memory Macro with Computation-Memory Aware Technique. 505-509 - Xinhuan Yang, Qianqian Sang, Chuanzheng Wang, Shuo Wang, Liang Wang, Yuanfu Zhao:
A Reliable and Economical Test Method for Semiconductor Device Aging. 520-523 - Zhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si:
A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model. 524-527 - Anni Cao, Xin Li, Liang Wang, Jianpeng Zhang, Chunliang Gou, Liquan Liu, Bi Wang, Xing Zhang, Yuanfu Zhao:
Total Dose and Single Event Effects on 16 Mbit Standalone Spin-Transfer Torque MRAM with 45 nm CMOS Technology. 528-531 - Xu Zhang, Fanyu Liu, Bo Li, Siyuan Chen, Yang Huang, Jiangjiang Li, Jian Jiao, Tianchun Ye, Jiajun Luo:
The Synergetic Effects of Total Ionizing Dose and High Temperature on 180 nm DSOI Technology. 532-535 - Wenjian Wu, Yingqi Ma, Minghui Cai:
Design of Integrated Circuit Hard Defect Location System Based on Thermal Laser Stimulation. 536-540 - Tobias Habermann, Jonas Kühle, Martin Kumm, Anastasia Volkova:
Hardware-Aware Quantization for Multiplierless Neural Network Controllers. 541-545 - Wenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong:
FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat Arithmetic. 546-550 - M. Mahmudul Hasan Sajeeb, Loai G. Salem:
Frequency-Selective Limiting Using Automatic Gain Control of Stagger-Tuned N-Path Filters. 551-555 - Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang:
A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. 556-559 - Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma:
A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. 560-564 - Hao Wang, Zhongka Lin, Kaiming Zhong, Xiang Yi, Guangyin Feng, Yanjie Wang:
A 28GHz Current-mode Outphasing Power Amplifier with 23.3dBm Psat and 44.2% PAE in 40nm CMOS. 565-568 - Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang:
A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. 569-573 - Qin Duan, Zhi-Jian Chen, Fengyuan Mao, Yu Zou, Bin Li, Guangyin Feng, Yanjie Wang, Xiao-Ling Lin:
A 27-29.5GHz 6-Bit Phase Shifter with 0.67 -1.5 degrees RMS Phase Error in 65nm CMOS. 574-577 - Xinshun Ning, Hongyong Yang, Mengdi Zhang, Yanji Wang, Ye Zhao, Shushan Qiao:
Multi-type SRAM Test Structure with an Improved March LR Algorithm. 578-582 - Jindou Xin, Xiang Zhu, Yingqi Ma, Jianwei Han:
Design of SEL Self-Recovery Hardness for 90nm COTS Devices Using R-C-S Network with DC-DC Converter. 583-587 - Langtao Chen, Xin Zhou, Ying Wang, Ying Kong, Rubin Xie, Ling Peng, Yantu Mo, Ming Qiao, Bo Zhang:
Study on Single Event Burnout Effect for 18V LDMOS Based on 0.18µm Process Technology. 588-591 - Honglin Kuang, Yifan Zhao, Jun Han:
A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm. 592-595 - Xiang Li, Dongsheng Liu, Ang Hu, Aobo Li, Shuo Yang, Jiahao Lu, Jianming Lei:
A High Throughput and Configurable Pseudo-random Number Extension Generator for Lattice-based Post-quantum Cryptography. 596-600 - Tianyu Xu, Yijun Cui, Dongsheng Liu, Chenghua Wang, Weiqiang Liu:
Lightweight and Efficient Hardware Implementation for Saber Using NTT Multiplication. 601-605 - Hui-qin Li, Tao Chen, Ai-qing Wu, Chao-xing Xu, Wei Li, Longmei Nan:
High Efficient Architecture of Polynomial Multiplier with Variable Parameter Based on 2KNTT. 606-610 - Ruth O'Connor, Ayesha Khalid, Máire O'Neill, Weiqiang Liu:
Better Security Estimates for Approximate, IoT-Friendly R-LWE Cryptosystems. 611-615
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