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Publication search results
found 84 matches
- 2006
- Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Leandro Rosa, José Luís Güntzel, Ivan Saraiva Silva:
High throughput architecture for H.264/AVC forward transforms block. ACM Great Lakes Symposium on VLSI 2006: 320-323 - David Bañeres, Jordi Cortadella, Michael Kishinevsky:
Dominator-based partitioning for delay optimization. ACM Great Lakes Symposium on VLSI 2006: 67-72 - Ali Bastani, Charles A. Zukowski:
Monotonic static CMOS tradeoffs in sub-100nm technologies. ACM Great Lakes Symposium on VLSI 2006: 278-283 - Rashed Zafar Bhatti, Monty Denneau, Jeff Draper:
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. ACM Great Lakes Symposium on VLSI 2006: 198-203 - Talal Bonny, Jörg Henkel:
Using Lin-Kernighan algorithm for look-up table compression to improve code density. ACM Great Lakes Symposium on VLSI 2006: 259-265 - Hung Tien Bui, Yvon Savaria:
High speed differential pulse-width control loop based on frequency-to-voltage converters. ACM Great Lakes Symposium on VLSI 2006: 53-56 - Scott J. Campbell, Sunil P. Khatri:
Resource and delay efficient matrix multiplication using newer FPGA devices. ACM Great Lakes Symposium on VLSI 2006: 308-311 - Sathish Chandra, Francesco Regazzoni, Marcello Lajolo:
Hardware/software partitioning of operating systems: a behavioral synthesis approach. ACM Great Lakes Symposium on VLSI 2006: 324-329 - Jun-Da Chen, Zhi-Ming Lin:
A low-power and high-linear double-balanced switching mixer. ACM Great Lakes Symposium on VLSI 2006: 131-134 - Chuen-Song Chen, Jien-Chung Lo, Tian Xia:
An indirect current sensing technique for IDDQ and IDDT tests. ACM Great Lakes Symposium on VLSI 2006: 235-240 - Wei-Chung Cheng, Chain-Fu Chao:
Perception-guided power minimization for color sequential displays. ACM Great Lakes Symposium on VLSI 2006: 290-295 - Royce L. S. Ching, Evangeline F. Y. Young:
Shuttle mask floorplanning with modified alpha-restricted grid. ACM Great Lakes Symposium on VLSI 2006: 85-90 - Ayse K. Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli:
A simulation methodology for reliability analysis in multi-core SoCs. ACM Great Lakes Symposium on VLSI 2006: 95-99 - Yongmei Dai, Zhiyuan Yan, Ning Chen:
Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes. ACM Great Lakes Symposium on VLSI 2006: 312-315 - Hima B. Damecharla, Kamal K. Varma, Joan Carletta, Amy E. Bell:
FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency. ACM Great Lakes Symposium on VLSI 2006: 266-271 - Mohamed El-Nozahi, Yehia Massoud:
An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs. ACM Great Lakes Symposium on VLSI 2006: 353-356 - Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer:
SACI: statistical static timing analysis of coupled interconnects. ACM Great Lakes Symposium on VLSI 2006: 241-246 - Bo Fu, Qiaoyan Yu, Paul Ampadu:
Energy-delay minimization in nanoscale domino logic. ACM Great Lakes Symposium on VLSI 2006: 316-319 - Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino:
ISS-centric modular HW/SW co-simulation. ACM Great Lakes Symposium on VLSI 2006: 31-36 - Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222 - Daniel Große, Ulrich Kühne, Rolf Drechsler:
HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48 - Renqiu Huang, Ranga Vemuri:
Transformation synthesis for data intensive applications to FPGAs. ACM Great Lakes Symposium on VLSI 2006: 349-352 - Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich:
Performance verification of high-performance ASICs using at-speed structural test. ACM Great Lakes Symposium on VLSI 2006: 247-252 - Abhishek Jajoo, Michael Sperling, Tamal Mukherjee:
Synthesis of a wideband low noise amplifier. ACM Great Lakes Symposium on VLSI 2006: 57-62 - Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical gate delay calculation with crosstalk alignment consideration. ACM Great Lakes Symposium on VLSI 2006: 223-228 - Marios Kalathas, Dimitrios Voudouris, George K. Papakonstantinou:
A heuristic algorithm to minimize ESOPs for multiple-output incompletely specified functions. ACM Great Lakes Symposium on VLSI 2006: 357-361 - Chang Woo Kang, Massoud Pedram:
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs. ACM Great Lakes Symposium on VLSI 2006: 79-84 - Young-Jun Kim, Taewhan Kim:
HW/SW partitioning techniques for multi-mode multi-task embedded applications. ACM Great Lakes Symposium on VLSI 2006: 25-30 - Hosung (Leo) Kim, John Lillis, Milos Hrkic:
Techniques for improved placement-coupled logic replication. ACM Great Lakes Symposium on VLSI 2006: 211-216 - Joonsoo Kim, Michael Orshansky:
Towards formal probabilistic power-performance design space exploration. ACM Great Lakes Symposium on VLSI 2006: 229-234
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