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Publication search results
found 19 matches
- 2018
- Yang Zhang, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel:
Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design. ASYNC 2018: 26-27 - Oyinkuro Benafa, Danil Sokolov, Alex Yakovlev:
Loadable Kessels Counter. ASYNC 2018: 102-109 - Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe:
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. ASYNC 2018: 34-42 - Cuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland:
Data-Loop-Free Self-Timed Circuit Verification. ASYNC 2018: 51-58 - Shomit Das, Michael LeBeane, Bradford M. Beckmann, Greg Sadowski:
Case Study of Process Variation-Based Domain Partitioning of GPGPUs. ASYNC 2018: 119-120 - Sam Fok, Kwabena Boahen:
A Serial H-Tree Router for Two-Dimensional Arrays. ASYNC 2018: 78-85 - Matthias Függer, Attila Kinali, Christoph Lenzen, Ben Wiederhake:
Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. ASYNC 2018: 68-77 - Sophie Germain, Sylvain Engels, Laurent Fesquet:
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. ASYNC 2018: 28-29 - Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet:
Static Timing Analysis of Asynchronous Bundled-Data Circuits. ASYNC 2018: 110-118 - Christoph Hoppe, Jens Döge, Peter Reichel, Patrick Russell, Andreas Reichel, Peter Schneider:
A High Speed Asynchronous Multi Input Pipeline for Compaction and Transfer of Parallel SIMD Data. ASYNC 2018: 86-92 - Florian Huemer, Andreas Steininger:
Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. ASYNC 2018: 17-25 - Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda:
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ASYNC 2018: 1-8 - Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies:
Loihi Asynchronous Neuromorphic Research Chip. ASYNC 2018: 32-33 - Alberto Moreno, Jordi Cortadella:
State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization. ASYNC 2018: 9-16 - Ning Qiao, Giacomo Indiveri:
A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems. ASYNC 2018: 93-101 - Justin Reiher, Mark R. Greenstreet, Ian W. Jones:
Explaining Metastability in Real Synchronizers. ASYNC 2018: 59-67 - Danil Sokolov, Victor Khomenko, Alex Yakovlev, David Lloyd:
Design and Verification of Speed-Independent Circuits with Arbitration in Workcraft. ASYNC 2018: 30-31 - Ghaith Tarawneh, Andrey Mokhov:
Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools. ASYNC 2018: 43-50 - 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-5883-3 [contents]
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