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ORCIDDFT 2010: Kyoto, Japan
- 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-8447-8
Keynote I
- Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe:
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. 3
Session 1: Emerging Technologies
- Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi:
An Analytical Error Model for Pattern Clipping in DNA Self-Assembly. 7-15 - Payman Zarkesh-Ha, Ali Arabi M. Shahi:
Logic Gate Failure Characterization for Nanoelectronic EDA Tools. 16-23 - Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz:
Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration. 24-31
Session 2: Design for Fault Tolerance I
- Cristiana Bolchini
, Antonio Miele:
Reliability-Driven System-Level Synthesis of Embedded Systems. 35-43 - Salvatore Campagna, Moazzam Hussain, Massimo Violante:
Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications. 44-51 - Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi, Takeshi Hattori:
A Hardware-Oriented Fault-Tolerant Routing Algorithm for Irregular 2D-Mesh Network-on-Chip without Virtual Channels. 52-59 - Navaneeth Rameshan, Vijay Laxmi, Manoj Singh Gaur, Mushtaq Ahmed, Krishan Kumar Paliwal:
Minimal Path, Fault Tolerant, QoS Aware Routing with Node and Link Failure in 2-D Mesh NoC. 60-66
Invited Talk I
- Yasuo Sato:
Circuit Failure Prediction by Field Test - A New Task of Testing. 69-70
Session 3: Design for Fault Tolerance II
- Kazuteru Namba, Hideo Ito:
Soft Error Tolerant BILBO FF. 73-81 - Kunihito Yamamori, Keisuke Tashiro, Masamichi Kusano, Ikuo Yoshihara:
A Design of Self-Defect-Compensatable Hardware Neuron for Multi-layer Neural Networks. 82-89 - Mario Schölzel, Sebastian Müller:
Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data Paths. 90-98
Poster Session
- Marc Hunger, Sybille Hellebrand:
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 101-108 - Tomoyuki Nagase, Kenji Ichijo, Akiko Narita, Yoshio Yoshioka:
CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and Analysis. 109-114 - NurQamarina MohdNoor, Azilah Saparon, Yusrina Yusof:
Programmable MBIST Merging FSM and Microcode Techniques Using Macro Commands. 115-121 - Min-Ju Chan, Chun-Lung Hsu:
A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip. 122-128 - Ming Zhu, Liyi Xiao, Shuhao Li, Yanjing Zhang:
Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory. 129-135 - Chun-Lung Hsu, Chen-Wei Lan, Yu-Chih Lo, Yu-Sheng Huang:
Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications. 136-143 - Nor Zaidi Haron, Said Hamdioui:
High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories. 144-151 - Mahroo Zandrahimi, Alireza Zarei, Hamid R. Zarandi:
A Probabilistic Method to Detect Anomalies in Embedded Systems. 152-159 - Osnat Keren, Ilya Levin, Mark G. Karpovsky:
Duplication Based One-to-Many Coding for Trojan HW Detection. 160-166 - Srikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth:
SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements. 167-171 - Tatsuya Suto, Kenji Ichijo, Yoshio Yoshioka:
Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System. 172-179 - Nor Azura Zakaria, Edward V. Bautista Jr., Suhaimi Bahisham Jusoh, Weng Fook Lee, Xiaoqing Wen:
Case Studies on Transition Fault Test Generation for At-speed Scan Testing. 180-188
Session 4: Design for Fault Tolerance III
- Cristiana Bolchini, Luca Fossati, David Merodio Codinachs, Antonio Miele, Chiara Sandionigi:
A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms. 191-199 - Eduardo Luis Rhod, Luca Sterpone, Luigi Carro:
A New Soft-Error Resilient Voltage-Mode Quaternary Latch. 200-208 - Dan Zhu, Tun Li, Sikun Li:
An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits. 209-217 - Hassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi:
A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs. 218-224
Keynote II
- Takashi Aikyo:
Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau. 227
Session 5: Yield Analysis and Dependability I
- Glenn H. Chapman, Jenny Leung, Israel Koren, Zahava Koren:
Tradeoffs in Imager Design with Respect to Pixel Defect Rates. 231-239 - Pilin Junsangsri, Fabrizio Lombardi:
Time/Temperature Degradation of Solar Cells under the Single Diode Model. 240-248 - Anant Narayan Hariharan, Salvatore Pontarelli, Marco Ottavi, Fabrizio Lombardi:
Modeling Open Defects in Nanometric Scale CMOS. 249-257
Invited Talk II
- Xiaoqing Wen:
Low-Power Testing for Low-Power Devices. 261
Session 6: Yield Analysis and Dependability II
- Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman:
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. 265-272 - Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz:
Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance. 273-279 - Kazuteru Namba, Masatoshi Sakata, Hideo Ito:
Single Event Induced Double Node Upset Tolerant Latch. 280-288 - Geunho Cho, Fabrizio Lombardi, Yong-Bin Kim:
Modelling a CNTFET with Undeposited CNT Defects. 289-296
Keynote III
- Nobuyasu Kanekawa:
Industrial Approach for Dependability. 299
Session 7: Testing and Design for Test
- Yoshiyuki Nakamura, Masashi Tanaka:
A Multi-dimensional Iddq Testing Method Using Mahalanobis Distance. 303-309 - Luca Amati, Cristiana Bolchini, Fabio Salice:
Test Selection Policies for Faster Incremental Fault Detection. 310-318 - Vijay K. Jain, Glenn H. Chapman:
Massively Deployable Intelligent Sensors for the Smart Power Grid. 319-327
Session 8: BIST and On-chip Test Generation
- Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen:
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. 331-339 - Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang:
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. 340-348 - Irith Pomeranz, Sudhakar M. Reddy:
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. 349-357 - Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang:
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. 358-366
Invited Talk III
- Noriaki Takagi:
A Study of eSRAM Testability. 369
Session 9: Error Detection and Correction
- Kensuke Tai, Masato Kitakami:
Prolongation of Lifetime and the Evaluation Method of Dependable SSD. 373-381 - Bishnu Prasad Das, Hidetoshi Onodera:
Warning Prediction Sequential for Transient Error Prevention. 382-390 - Daniele Rossi, Martin Omaña, Cecilia Metra:
Transient Fault and Soft Error On-die Monitoring Scheme. 391-398 - Bijan Ansari, Ingrid Verbauwhede:
A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite Fields. 399-407
Session 10: Error Detection and Correction
- Daisaku Seto, Minoru Watanabe:
Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays. 411-419 - Salvatore Pontarelli, Marco Ottavi, Adelio Salsano:
Error Detection and Correction in Content Addressable Memories. 420-428 - Navid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori:
Online Multiple Fault Detection in Reversible Circuits. 429-437 - Erik MacLean, Vijay K. Jain:
Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip. 438-446
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