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2020 – today
- 2024
[j42]He Liu, Jiaqiang Li, Liyi Xiao
, Tianqi Wang, Jie Li:
SET-detection low complexity burst error correction codes for SRAM protection. Integr. 98: 102212 (2024)- [i7]Fangfa Fu, Wenyu Zhang, Zesong Jiang, Zhiyu Zhu, Guoyu Li, Bing Yang, Cheng Liu, Liyi Xiao, Jinxiang Wang, Huawei Li, Xiaowei Li:
SigDLA: A Deep Learning Accelerator Extension for Signal Processing. CoRR abs/2407.12565 (2024) - 2023
- [j41]Xiaoqiang Liu, Mingxue Li, Xinkai Chen, Yiheng Zhao, Liyi Xiao, Yufeng Zhang:
A Compact RF Energy Harvesting Wireless Sensor Node with an Energy Intensity Adaptive Management Algorithm. Sensors 23(20): 8641 (2023) - 2022
- [j40]Linzhe Li, Liyi Xiao, He Liu, Zhigang Mao:
Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits. IEEE Access 10: 64161-64171 (2022) - [j39]Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang:
A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors. IEEE Access 10: 89000-89010 (2022) - [j38]Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang:
A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2721-2729 (2022) - 2021
- [j37]Chunhua Qi, Yanqing Zhang, Guoliang Ma, Chaoming Liu, Tianqi Wang, Liyi Xiao, Mingxue Huo, Guofu Zhai:
Design of a high-performance 12T SRAM cell for single event upset tolerance. Sci. China Inf. Sci. 64(11) (2021) - [j36]Jie Li, Pedro Reviriego, Shanshan Liu, Liyi Xiao, Fabrizio Lombardi:
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH). Integr. 81: 246-253 (2021) - [j35]Hongchen Li, Liyi Xiao, Chunhua Qi, Jie Li:
Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4170-4181 (2021) - [j34]Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Haotian Wu:
Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes. IEEE Trans. Emerg. Top. Comput. 9(2): 651-663 (2021) - 2020
- [j33]Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi:
Scheme for periodical concurrent fault detection in parallel CRC circuits. IET Comput. Digit. Tech. 14(2): 80-85 (2020) - [j32]Peng Gao, Qiquan Zhang, Fei Wang, Liyi Xiao, Hamido Fujita, Yan Zhang:
Learning reinforced attentional representation for end-to-end visual tracking. Inf. Sci. 517: 52-67 (2020) - [j31]Peng Gao, Ruyue Yuan, Fei Wang, Liyi Xiao, Hamido Fujita, Yan Zhang:
Siamese attentional keypoint network for high performance visual tracking. Knowl. Based Syst. 193: 105448 (2020) - [j30]Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Linzhe Li:
An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA. IEEE Trans. Reliab. 69(2): 430-439 (2020) - [c32]Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro:
Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes. DCIS 2020: 1-5
2010 – 2019
- 2019
- [j29]Mingxue Huo, Guoliang Ma, Bin Zhou, Liyi Xiao, Chunhua Qi, Yanqing Zhang, Jianning Ma, Yinghun Piao, Tianqi Wang:
Single-event upset prediction in static random access memory cell account for parameter variations. Sci. China Inf. Sci. 62(6): 69404:1-69404:3 (2019) - [j28]Jiaqiang Li, Pedro Reviriego, Liyi Xiao:
Low Delay 3-Bit Burst Error Correction Codes. J. Electron. Test. 35(3): 413-420 (2019) - [j27]Xuebing Cao, Liyi Xiao, Jie Li, Rongsheng Zhang, Shanshan Liu, Jinxiang Wang:
A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1109-1122 (2019) - [c31]Hongchen Li, Liyi Xiao, Jie Li, He Liu:
Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology. ASICON 2019: 1-4 - [c30]Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao:
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. ASICON 2019: 1-4 - [c29]Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang:
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network. ASICON 2019: 1-4 - [c28]Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Alexander Klockmann:
Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction. DFT 2019: 1-4 - [c27]Shanshan Liu, Pedro Reviriego, Kazuteru Namba, Salvatore Pontarelli, Liyi Xiao, Fabrizio Lombardi:
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells. DFT 2019: 1-4 - [c26]Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Tianqi Wang:
Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs. ICICDT 2019: 1-4 - [c25]Peng Gao, Yipeng Ma, Ruyue Yuan, Liyi Xiao, Fei Wang:
Learning Cascaded Siamese Networks for High Performance Visual Tracking. ICIP 2019: 3078-3082 - [c24]Jiaqiang Li, Pedro Reviriego, Costas Argyrides, Liyi Xiao:
Efficient Concurrent Error Detection for SEC-DAEC Encoders. IOLTS 2019: 165-170 - [i6]Peng Gao, Yipeng Ma, Ruyue Yuan, Liyi Xiao, Fei Wang:
Siamese Attentional Keypoint Network for High Performance Visual Tracking. CoRR abs/1904.10128 (2019) - [i5]Peng Gao, Yipeng Ma, Ruyue Yuan, Liyi Xiao, Fei Wang:
Learning Cascaded Siamese Networks for High Performance Visual Tracking. CoRR abs/1905.02857 (2019) - [i4]Peng Gao, Qiquan Zhang, Liyi Xiao, Yan Zhang, Fei Wang:
Learning Reinforced Attentional Representation for End-to-End Visual Tracking. CoRR abs/1908.10009 (2019) - 2018
- [j26]Peng Gao, Yipeng Ma, Chao Li, Ke Song, Yan Zhang, Fei Wang, Liyi Xiao:
Adaptive Object Tracking with Complementary Models. IEICE Trans. Inf. Syst. 101-D(11): 2849-2854 (2018) - [j25]Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao, Yan Zhang:
High performance visual tracking with circular and structural operators. Knowl. Based Syst. 161: 240-253 (2018) - [j24]Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro, Liyi Xiao:
Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes. Microelectron. Reliab. 81: 167-173 (2018) - [j23]Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Chunhua Qi, Jiaqiang Li, Mingjiang Wang:
A fast fault injection platform of multiple SEUs for SRAM-based FPGAs. Microelectron. Reliab. 82: 147-152 (2018) - [j22]Jiaqiang Li, Liyi Xiao, Pedro Reviriego, Rongsheng Zhang:
Efficient Implementations of 4-Bit Burst Error Correction for Memories. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 2037-2041 (2018) - [j21]Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li:
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 221-229 (2018) - [j20]Jing Guo, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao:
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 991-994 (2018) - [c23]Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao:
Large Margin Structured Convolution Operator for Thermal Infrared Object Tracking. ICPR 2018: 2380-2385 - [c22]Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Jiaqiang Li, Jinxiang Wang:
Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm. IOLTS 2018: 165-170 - [i3]Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao:
Large Margin Structured Convolution Operator for Thermal Infrared Object Tracking. CoRR abs/1804.07006 (2018) - [i2]Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao:
A Complementary Tracking Model with Multiple Features. CoRR abs/1804.07459 (2018) - [i1]Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao, Yan Zhang:
High Performance Visual Tracking with Circular and Structural Operators. CoRR abs/1804.08208 (2018) - 2017
- [j19]Shanshan Liu, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro, Liyi Xiao:
Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016). Microelectron. Reliab. 69: 126-129 (2017) - [j18]Shanshan Liu, Pedro Reviriego, Liyi Xiao, Juan Antonio Maestro:
A method to recover critical bits under a double error in SEC-DED protected memories. Microelectron. Reliab. 73: 92-96 (2017) - [j17]Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro:
A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes. IEEE Trans. Reliab. 66(2): 518-528 (2017) - [j16]Jing Guo, Lei Zhu, Wenyi Liu, Hai Huang, Shanshan Liu, Tianqi Wang, Liyi Xiao, Zhigang Mao:
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1593-1600 (2017) - [c21]Liyi Xiao, Chunhua Qi, Tianqi Wang, Hongchen Li, Jiaqiang Li:
Low-cost resilient radiation hardened flip-flop design. ASICON 2017: 222-225 - [c20]Rongsheng Zhang, Liyi Xiao, Jie Li:
A fast and accurate fault injection platform for SRAM-based FPGAs. ASICON 2017: 359-362 - [c19]Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li, Tianqi Wang:
A method to estimate cross-section of circuits at RTL levels. ASICON 2017: 363-366 - [c18]Shanshan Liu, Liyi Xiao, Xuebing Cao, Zhigang Mao:
Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability. ASP-DAC 2017: 87-92 - [c17]Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao:
Low redundancy matrix-based codes for adjacent error correction with parity sharing. ISQED 2017: 76-80 - [c16]Chunhua Qi, Liyi Xiao, Mingxue Huo, Tianqi Wang, Rongsheng Zhang, Xuebing Cao:
A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications. ISQED 2017: 161-165 - 2016
- [j15]Shanshan Liu, Liyi Xiao, Zhigang Mao:
Extend orthogonal Latin square codes for 32-bit data protection in memory applications. Microelectron. Reliab. 63: 278-283 (2016) - [j14]Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro:
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1603-1606 (2016) - 2015
- [j13]Chunhua Qi, Liyi Xiao, Jing Guo, Tianqi Wang:
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology. Microelectron. Reliab. 55(6): 863-872 (2015) - [j12]Jing Guo, Liyi Xiao, Tianqi Wang, Shanshan Liu, Xu Wang, Zhigang Mao:
Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology. IEEE Trans. Reliab. 64(2): 596-602 (2015) - [c15]Shanshan Liu, Liyi Xiao, Jing Guo, Zhigang Mao:
Fault Secure Encoder and Decoder Designs for Matrix Codes. CAD/Graphics 2015: 181-185 - [c14]Tianqi Wang, Liyi Xiao, Mingxue Huo, Chunhua Qi, Shanshan Liu:
Novel technique for P-hit single-event transient mitigation using enhance dummy transistor. ISQED 2015: 243-249 - [c13]Liyi Xiao, Jiaqiang Li, Jie Li, Jing Guo:
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories. ISQED 2015: 485-489 - 2014
- [j11]Hai Huang, Liyi Xiao, Jiaming Liu:
CORDIC-Based Unified Architectures for Computation of DCT/IDCT/DST/IDST. Circuits Syst. Signal Process. 33(3): 799-814 (2014) - [j10]Hai Huang, Liyi Xiao:
CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation. Microelectron. J. 45(11): 1480-1488 (2014) - [j9]Jing Guo, Liyi Xiao, Zhigang Mao:
Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 1994-2001 (2014) - [j8]Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao:
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 127-135 (2014) - 2013
- [j7]Bin Zhou, Xin-chun Wu, Yu Sun, Tianqi Wang, Liyi Xiao:
A Low Power Built-in Self-Test Scheme Based on Overlapping Bit Swapping Linear Feedback Shift Register. J. Low Power Electron. 9(4): 519-526 (2013) - [j6]Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao:
Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs. IEEE Micro 33(6): 66-74 (2013) - [j5]Hai Huang, Liyi Xiao:
CORDIC Based Fast Radix-2 DCT Algorithm. IEEE Signal Process. Lett. 20(5): 483-486 (2013) - 2012
- [j4]Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao:
Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost. J. Low Power Electron. 8(1): 73-81 (2012) - 2011
- [j3]Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu:
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping. J. Electron. Test. 27(1): 43-56 (2011) - [j2]Ming Zhu, Liyi Xiao, Li Li Song, Yan Jing Zhang, Hong Wei Luo:
New Mix codes for multiple bit upsets mitigation in fault-secure memories. Microelectron. J. 42(3): 553-561 (2011) - [c12]Ming Zhu, Liyi Xiao, Hong Wei Luo:
New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory. VLSI-SoC 2011: 254-259 - 2010
- [c11]Ming Zhu, Liyi Xiao, Shuhao Li, Yanjing Zhang:
Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory. DFT 2010: 129-135 - [c10]Yu Sun, Liyi Xiao, Cong Shi:
DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current. ISCAS 2010: 3717-3720
2000 – 2009
- 2009
- [c9]Weiguang Sheng, Liyi Xiao, Zhigang Mao:
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. DAC 2009: 502-507 - 2008
- [c8]Hong Hong, Yi Ren, Ricai Tian, Liyi Xiao:
Electronic Shelf Label System based on public illuminating network. APCCAS 2008: 1103-1106 - [c7]Bei Cao, Liyi Xiao, Yongsheng Wang:
A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. DELTA 2008: 266-269 - [c6]Weiguang Sheng, Liyi Xiao, Zhigang Mao:
An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. DELTA 2008: 587-591 - [c5]Weiguang Sheng, Liyi Xiao, Zhigang Mao:
A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis. ICECS 2008: 766-769 - [c4]Weiguang Sheng, Liyi Xiao, Zhigang Mao:
Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. PRDC 2008: 17-23 - 2003
- [c3]Yongsheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye:
A Test Architecture for System-on-a-Chip. Asian Test Symposium 2003: 506 - 2002
- [j1]Liyi Xiao, Yizheng Ye, Bin Li:
A New Synchronization Algorithm for VHDL-AMS Simulation. J. Comput. Sci. Technol. 17(1): 28-37 (2002) - 2001
- [c2]Bin Li, Liyi Xiao, Yizheng Ye, Guoyong Huang:
CLUGGS and CLUCR-Two Matrix Solution Methods for General Circuit Simulation. Annual Simulation Symposium 2001: 78- - [c1]Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang:
A mixed-signal simulator for VHDL-AMS. ASP-DAC 2001: 287-292
Coauthor Index
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