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ORCIDDFT 2012: Austin, TX, USA
- 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-3043-5
- Mafalda Cortez
, Apurva Dargar, Said Hamdioui, Geert Jan Schrijen:
Modeling SRAM start-up behavior for Physical Unclonable Functions. 1-6 - Ke Huang, John M. Carulli Jr., Yiorgos Makris:
Parametric counterfeit IC detection via Support Vector Machines. 7-12 - Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor:
Path-delay fingerprinting for identification of recovered ICs. 13-18 - Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba:
Using partial masking in X-chains to increase output compaction for an X-canceling MISR. 19-24 - Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the development of Software-Based Self-Test methods for VLIW processors. 25-30 - Marcelo de Souza Moraes, Marcos Barcellos Hervé, Marcelo Lubaszewski:
Low pin count DfT technique for RFID ICs. 31-36 - Irith Pomeranz:
Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults. 37-42 - Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede:
A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures. 43-48 - Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker:
#SAT-based vulnerability analysis of security components - A case study. 49-54 - Xinmu Wang, Tatini Mal-Sarkar, Aswin Raghav Krishna, Seetharam Narasimhan, Swarup Bhunia:
Software exploitable hardware Trojans in embedded processor. 55-58 - Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh:
Minimization of Trojan footprint by reducing Delay/Area impact. 59-62 - Juan Carlos Martínez Santos, Yunsi Fei:
Designing and implementing a Malicious 8051 processor. 63-66 - Yang Lu, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi:
On the design of two single event tolerant slave latches for scan delay testing. 67-72 - Jianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han:
Hardening a memory cell for low power operation by gate leakage reduction. 73-78 - Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans:
Single event upset tolerance in flip-flop based microprocessor cores. 79-84 - Alireza Rohani, Hans G. Kerkhoff:
An on-line soft error mitigation technique for control logic of VLIW processors. 85-91 - Chuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu:
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors. 92-97 - Yifat Manzor, Osnat Keren:
Amalgamated q-ary codes for multi-level flash memories. 98-103 - Sreenivas Gangadhar, Spyros Tragoudas:
Accurate calculation of SET propagation probability for hardening. 104-108 - Adam Watkins, Spyros Tragoudas:
Transient pulse propagation using the Weibull distribution function. 109-114 - Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone:
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs. 115-120 - Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella:
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. 121-125 - Da Cheng, Sandeep K. Gupta:
A systematic methodology to improve yield per area of highly-parallel CMPs. 126-133 - Fabrizio Lombardi, Nohpill Park, Haider A. F. Almurib, T. Nandha Kumar:
On the multiple fault detection of a nano crossbar. 134-139 - Ali Arabi M. Shahi, Payman Zarkesh-Ha:
Prediction of gate delay variation for CNFET under CNT density variation. 140-145 - Irith Pomeranz:
Built-in generation of multi-cycle broadside tests. 146-151 - Gabriel L. Nazar, Luigi Carro:
Fast single-FPGA fault injection platform. 152-157 - Seyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor:
Incorporating parameter variations in BTI impact on nano-scale logical gates analysis. 158-163 - Glenn H. Chapman, Rohit Thomas, Israel Koren, Zahava Koren:
Relating digital imager defect rates to pixel size, sensor area and ISO. 164-169 - Kyu-Nam Shim, Jiang Hu:
A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience. 170-177 - Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba:
Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly. 178-181 - Vadim Geurkov:
Optimal choice of arithmetic compactors for mixed-signal systems. 182-186 - Kazuteru Namba, Takashi Katagiri, Hideo Ito:
Dual-edge-triggered FF with timing error detection capability. 187-192 - Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Improving small-delay fault coverage for on-chip delay measurement. 193-198 - Martin Omaña, Daniele Rossi, G. Collepalumbo, Cecilia Metra, Fabrizio Lombardi:
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. 199-204 - Mohammad Maghsoudloo, Hamid R. Zarandi:
Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols. 205-210 - Rance Rodrigues, Israel Koren, Sandip Kundu:
A mechanism to verify cache coherence transactions in multicore systems. 211-216 - Tomohiro Yoneda, Masashi Imai:
Dependable routing in multi-chip NoC platforms for automotive applications. 217-224 - Richard A. Guinee:
A novel pseudonoise tester for transmission line fault location and identification using pseudorandom binary sequences. 225-232 - Oscar Acevedo, Dimitri Kagaris:
Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG. 233-238 - Irith Pomeranz:
Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests. 239-244
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