default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISPD 2015: Monterey, CA, USA
- Azadeh Davoodi, Evangeline F. Y. Young:
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015. ACM 2015, ISBN 978-1-4503-3399-3
Welcome and Keynote Address
- Karim Arabi, Kambiz Samadi, Yang Du:
3D VLSI: A Scalable Integration Beyond 2D. 1-7
Advanced Placement and Analog Design
- Ulrich Brenner, Anna Hermann, Nils Hoppmann, Philipp Ochsendorf:
BonnPlace: A Self-Stabilizing Placement Framework. 9-16 - Sungmin Bae, Hyung-Ock Kim, Jung Yun Choi, Jaehong Park:
Coarse-grained Structural Placement for a Synthesized Parallel Multiplier. 17-24 - Po-Hsun Wu, Mark Po-Hung Lin
, Xin Li, Tsung-Yi Ho:
Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment. 25-31 - Jürgen Scheible, Jens Lienig:
Automation of Analog IC Layout: Challenges and Solutions. 33-40
Learning Physical Design
- Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi, Shih-Chieh Chang:
Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation. 41-48 - Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai:
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. 49-56 - Li-C. Wang, Malgorzata Marek-Sadowska:
Machine Learning in Simulation-Based Analysis. 57-64
DFM
- H.-S. Philip Wong, He Yi, Maryann C. Tung, Kye Okabe:
Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning. 65-66 - Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, Ting-Chi Wang:
A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography. 67-74 - Tao Lin, Chris C. N. Chu:
TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints. 75-80
Dinner Banquet
- Dean Drako:
Concept & Research to Revenue: An Entrepreneurial Story. 81
Tuesday Keynote Address
- Rob A. Rutenbar:
Analog Circuit and Layout Synthesis Revisited. 83
Clocking and Power
- Rickard Ewetz, Cheng-Kok Koh:
A Useful Skew Tree Framework for Inserting Large Safety Margins. 85-92 - Chang Xu, Peixin Li, Guojie Luo, Yiyu Shi, Iris Hui-Ru Jiang:
Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging. 93-100 - Farid N. Najm:
Physical Design Challenges in the Chip Power Distribution Network. 101
Physical Design and Beyond
- Tsung-Wei Huang, Martin D. F. Wong:
Accelerated Path-Based Timing Analysis with MapReduce. 103-110 - Ali Abbasinasab, Malgorzata Marek-Sadowska:
Blech Effect in Interconnects: Applications and Design Guidelines. 111-118 - Qiang Han, Jianghao Guo, Qiang Xu, Wen-Ben Jone:
On Resilient System Performance Binning. 119-125 - Olivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, Ogun Turkyilmaz, Sébastien Thuries, Fabien Clermidy:
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges. 127
Commemoration for Prof. Kurt Antreich
- Martin D. F. Wong:
Early Days of Circuit Placement. 129 - Hans Eisenmann:
Force-Directed Placement of VLSI Circuits. 131-132 - Ulf Schlichtmann:
Beyond GORDIAN and Kraftwerk: EDA Research at TUM. 133-140
Placement and Contest
- Chrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos:
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. 141-148 - Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen:
Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability. 149-156 - Ismail S. Bustany, David G. Chinnery, Joseph R. Shinnerl, Vladimir Yutsis:
ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement. 157-164
FreePDK
- Kirti Bhanushali, W. Rhett Davis:
FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology. 165-170 - Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen:
Open Cell Library in 15nm FreePDK Technology. 171-178 - Michiel Oostindie, Coby Zelnik, Maarten Berkens:
Design Rule Management and its Applications in 15nm FreePDK Technology. 179-183 - Jody Maick Matos, Augusto Neutzling, Renato P. Ribas, André Inácio Reis:
A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design. 185-192
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 01:26 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
