Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID6th MCSoC 2012: Fukushima, Japan
- IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2012, Fukushima, Japan, September 20-22, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-2535-6
- Takuya Otsuka, Takashi Aoki, Eiichi Hosoya, Akira Onozawa:
An Image Recognition System for Multiple Video Inputs over a Multi-FPGA System. 1-7 - Junko Tazawa, Yuichi Okuyama, Yuichi Yaguchi, Toshiaki Miyazaki, Ryuichi Oka, Kenichi Kuroda:
Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming. 8-15 - Shizuka Ishikawa, Asuka Tanaka, Toshiaki Miyazaki:
Hardware Accelerator for BLAST. 16-22 - Xiaoping Huang, Xiaoya Fan, Shengbing Zhang, Yuhui Chen:
DLWAP-buffer: A Novel HW/SW Architecture to Alleviate the Cache Coherence on Streaming-like Data in CMP. 23-28 - Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
On-chip Communication Buffer Architecture Optimization Considering Bus Width. 29-36 - Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga:
Throttling Control for Bufferless Routing in On-chip Networks. 37-44 - Kunio Takaya:
Transputer-like Multicore Digital Signal Processing on the Array of ARM Cortex-M0 Microprocessors. 45-50 - Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid:
FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations. 51-58 - Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. 59-66 - Muhammad Adeel Tajammul, Muhammad Ali Shami
, Ahmed Hemani:
Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture. 67-74 - Naohito Nakasato, Hiroshi Daisaka, Toshiyuki Fukushige, Atsushi Kawai, Junichiro Makino, Tadashi Ishikawa, Fukuko Yuasa:
GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/Octuple-Precision Arithmetic Operation on a Structured ASIC and an FPGA. 75-83 - Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga:
Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA. 84-91 - Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki:
Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor. 92-99 - Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura:
An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip. 100-106 - Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion. 107-112 - Zheng Zhou, Junjun Gu, Gang Qu:
Scheduling for Multi-core Processor under Process and Temperature Variation. 113-120 - Li Wang, Jing Liu, Jingtong Hu, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Optimal Assignment for Tree-Structure Task Graph on Heterogeneous Multicore Systems Considering Time Constraint. 121-127 - Xuanya Li, Linlin Ci, Minghua Yang, Hongyu Wei, Chengping Tian, Bin Cheng:
Multi-decision Making Based PSO Optimization in Airborne Mobile Sensor Network Deployment. 128-134 - Hong Yao, Zheng Zhao, Huawei Huang, Lei Cong:
A Novel Data Transfer Scheme of Smart Grid and DTN. 135-138 - Junbo Wang, Zixue Cheng, Isao Nishiyama, Yinghui Zhou:
Design of a Safety Confirmation System Integrating Wireless Sensor Network and Smart Phones for Disaster. 139-143 - Xiang Li, Xuanya Li:
Accurate Coverage of Complex Targets in Three-Dimensional Mobile Sensor Networks. 144-150 - Zhenhe Ma, Tao Xu, Linlin Du, Zhongdi Chu, Jiangtao Lv, Fengwen Wang:
Early Stage Chick Embryonic Heart Outflow Tract Flow Measurement Using High Speed 4D Optical Coherence Tomography. 151-154 - Wenfeng Shen, Liang Wang, Jie Li, Weimin Xu, Daming Wei, Xin Zhu:
Load-Prediction Parallelization for Computer Simulation of Electrocardiogram Based on GPU. 155-158 - Nicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi:
Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels. 159-166 - Akram Ben Ahmed, Abderazek Ben Abdallah:
LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture. 167-174 - Yu-Hsin Kuo, Po-An Tsai, Hao-Ping Ho, En-Jui Chang, Hsien-Kai Hsin, An-Yeu Andy Wu:
Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems. 175-182 - Akira Imakura, Tetsuya Sakurai, Kohsuke Sumiyoshi, Hideo Matsufuru:
An Auto-Tuning Technique of the Weighted Jacobi-Type Iteration Used for Preconditioners of Krylov Subspace Methods. 183-190 - Satoshi Ito, Satoshi Ohshima, Takahiro Katagiri:
SSG-AT: An Auto-tuning Method of Sparse Matrix-vector Multiplicataion for Semi-structured Grids - An Adaptation to OpenFOAM. 191-197 - Kazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin:
Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPU. 198-204 - Yaohung M. Tsai, Weichung Wang, Ray-Bing Chen:
Tuning Block Size for QR Factorization on CPU-GPU Hybrid Systems. 205-211
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-06-19 20:47 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
