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ORCID41st MICRO 2008: Lake Como, Italy
- 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy. IEEE Computer Society 2008, ISBN 978-1-4244-2836-6
Keynote 1
- Charles R. Moore:
Microarchitecture in the system-level integration era.
Instruction-Level Parallelism
- David E. Shaw:
Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins. - Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos:
Temporal instruction fetch streaming. 1-10 - Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez
, Adrián Cristal, Mateo Valero:
A distributed processor state management architecture for large-window processors. 11-22 - Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley:
Strategies for mapping dataflow blocks to distributed hardware. 23-34
Cache Coherence and Cache Modeling
- Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti:
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence. 35-46 - Arun Raghavan, Colin Blundell, Milo M. K. Martin:
Token tenure: PATCHing token counting using directory-based cache coherence. 47-58 - Xi E. Chen, Tor M. Aamodt:
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. 59-70
Cache Architectures for Security and Availability
- Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan:
Implementing high availability memory with a duplication cache. 71-82 - Zhenghong Wang, Ruby B. Lee:
A novel cache architecture with enhanced performance and security. 83-93 - Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood:
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags. 94-105
Reliability, Availability, Security
- Vikas R. Vasisht, Hsien-Hsin S. Lee:
SHARK: Architectural support for autonomic protection against stealth by rootkit exploits. 106-116 - Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie:
Testudo: Heavyweight security analysis via statistical sampling. 117-128 - Abhishek Tiwari, Josep Torrellas:
Facelift: Hiding and slowing down aging in multicores. 129-140 - Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke:
The StageNet fabric for constructing resilient multicore systems. 141-151
Embedded and Special Purpose Architectures
- Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner:
From SODA to scotch: The evolution of a wireless baseband processor. 152-163 - Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel:
Tradeoffs in designing accelerator architectures for visual computing. 164-175 - Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary K. Vernon, William R. Mark:
Toward a multicore architecture for real-time ray-tracing. 176-187 - Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott Miller, Gokhan Memik, Peter A. Dinda, Robert P. Dick:
Power to the people: Leveraging human physiological traits to control microprocessor frequency. 188-199
Memory and Cache Architectures
- Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt:
Prefetch-Aware DRAM Controllers. 200-209 - Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu:
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. 210-221 - Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger:
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency. 222-233
Transactions and Runtime Systems
- Luke Yen, Stark C. Draper, Mark D. Hill:
Notary: Hardware techniques to enhance signatures. 234-245 - Hany E. Ramadan, Christopher J. Rossbach, Emmett Witchel:
Dependence-aware transactional memory for increased concurrency. 246-257 - Livio Soares, David K. Tam, Michael Stumm:
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer. 258-269
Modeling, Simulation and Verification
- Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks:
CPR: Composable performance regression for scalable multiprocessor models. 270-281 - Kypros Constantinides, Onur Mutlu, Todd M. Austin:
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. 282-293 - Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz:
Verification of chip multiprocessor memory systems using a relaxed scoreboard. 294-305
Multicore and Multithreading
- Alok Garg, Michael C. Huang:
A performance-correctness explicitly-decoupled architecture. 306-317 - Ramazan Bitirgen, Engin Ipek, José F. Martínez:
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. 318-329 - Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta:
Copy or Discard execution model for speculative parallelization on multicores. 330-341
Interconnects
- Amit Kumar, Li-Shiuan Peh, Niraj K. Jha:
Token flow control. 342-353 - Yuho Jin, Ki Hwan Yum, Eun Jung Kim:
Adaptive data compression for high-performance low-power on-chip networks. 354-363 - Samuel Rodrigo, José Flich, José Duato, Mark Hummel:
Efficient unicast and multicast support for CMPs. 364-375 - M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam:
Power reduction of CMP communication networks via RF-interconnects. 376-387
Process Variation
- Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Evaluating the effects of cache redundancy on profit. 388-398 - Xin Fu, Tao Li, José A. B. Fortes:
NBTI tolerant microarchitecture design in the presence of process variation. 399-410 - Eric Chun, Zeshan Chishti, T. N. Vijaykumar:
Shapeshifter: Dynamically changing pipeline width and speed to address process variations. 411-422 - Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas:
EVAL: Utilizing processors with variation-induced timing errors. 423-434
Circuits and Microarchitectures
- Wangyuan Zhang, Tao Li:
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology. 435-446 - Renée St. Amant, Daniel A. Jiménez, Doug Burger:
Low-power, high-performance analog neural branch prediction. 447-458 - Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztián Flautner:
Reconfigurable energy efficient near threshold cache architectures. 459-470
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