default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID31st VLSI-SOC 2023: Dubai, United Arab Emirates
- 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023. IEEE 2023, ISBN 979-8-3503-2599-7
- Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza:
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. 1-6 - Sejin Lim, Hyunjun Kim, Kyungbae Jang, Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay, Hwajeong Seo:
Optimized Quantum Circuit Implementation of Payoff Function. 1-6 - Hossein Taji, José Miranda, Miguel Peón-Quirós, Szabolcs Balási, David Atienza:
Dynamic Scheduling for Event-Driven Embedded Industrial Applications. 1-6 - Anton Datsuk, Philip Ostrovskyy, Frank Vater, Christian Wieden:
Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform. 1-6 - Paolo Bernardi, Giorgio Insinga, Nima Kolahimahmoudi
:
A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test. 1-6 - Rassul Bairamkulov, Alessandro Tempia Calvino, Giovanni De Micheli:
Synthesis of SFQ Circuits with Compound Gates. 1-6 - Shubham Kumar, Paul R. Genssler, Somaya Mansour, Yogesh Singh Chauhan, Hussam Amrouch:
Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration. 1-6 - Hassen Aziza, Cristian Zambelli, Said Hamdioui, Sumit Diware, Rajendra Bishnoi, Anteneh Gebregiorgis:
On the Reliability of RRAM-Based Neural Networks. 1-8 - Jean-Philippe Noël, Emanuele Valea, Laurent Grenouillet, B. Chapuis, Clément Fisher, A. Recoquillay, Bastien Giraud:
Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems. 1-6 - Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet:
Method for Data-Driven Pruning in Micropipeline Circuits. 1-6 - Muhammad Jawad Shakil, Uzair Ahmed, Jafar Hussain, Hassan Saif, Rashad Ramzan:
A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter. 1-6 - Dheemanth Joshi, Aniket Arun Gangotri, Sai Pranay Chennamsetti, Gautham Bolar, Ganesan Thiagarajan, Sanjeev Gurugopinath:
A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology. 1-6 - Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Mapping of CNNs on multi-core RRAM-based CIM architectures. 1-6 - Hanning Chen, Yeseong Kim, Elaheh Sadredini, Saransh Gupta, Hugo Latapie, Mohsen Imani:
Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration. 1-6 - Solomon Michael Serunjogi, Mihai Sanduleanu:
3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect. 1-4 - Gabriel Rutsch, Konrad Maier, Wolfgang Ecker:
FPGA-implementation techniques to efficiently test application readiness of mixed-signal products. 1-6 - Foroozan Karimzadeh, Mohsen Imani, Bahar Asgari, Ningyuan Cao, Yingyan Lin, Yan Fang:
Memory-Based Computing for Energy-Efficient AI: Grand Challenges. 1-8 - Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs. 1-6 - Ziyang Ye, Makoto Ikeda:
Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks. 1-6 - Suman Deb, Anupam Chattopadhyay, Avi Mendelson:
A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion. 1-6 - Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay:
PR-PUF: A Reconfigurable Strong RRAM PUF. 1-6 - Safiullah Khan, Ayesha Khalid, Ciara Rafferty, Yasir Ali Shah, Máire O'Neill, Wai-Kong Lee, Seong Oun Hwang:
Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators. 1-6 - Sagheer Ahmed, Jayesh Ambulkar, Debabrata Mondal, Ambika Prasad Shah:
Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications. 1-6 - Imlijungla Longchar, Hemangee K. Kapoor:
ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference. 1-6 - Chun-Jen Tsai, Chun Wei Chao, Sheng-Di Hong:
Integrated Dynamic Memory Manager for a RISC-V Processor. 1-5 - Shayesteh Masoumian, Roel Maes, Rui Wang, Karthik Keni Yerriswamy, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil:
Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. 1-6 - Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy:
Noise modeling using look-up tables and DC measurements for cryogenic applications. 1-6 - Yiyang Yu, Atif Shamim:
Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip. 1-5 - Cédric Marchand, Alban Nicolas, Paul-Antoine Matrangolo, David Navarro, Alberto Bosio, Ian O'Connor:
FeFET based Logic-in-Memory design methodologies, tools and open challenges. 1-6 - Omar Numan, Martin Andraud, Kari Halonen:
A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing. 1-6 - Umair F. Siddiqi, Gary William Grewal, Shawki Areibi:
A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms. 1-6 - Hala Ibrahim, Haytham Azmi, M. Watheq El-Kharashi, Mona Safar:
Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification. 1-6 - Junjie Li, Youming Zhang, Yunqi Cao, Xusheng Tang, Fengyi Huang:
A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer. 1-4 - Rafael Medina, Darong Huang, Giovanni Ansaloni, Marina Zapater, David Atienza:
REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal. 1-6 - Shahid Jamil, Muhammad Usman, Muhammad Jawad Shakil, Jafar Hussain, Rashad Ramzan:
Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications. 1-6 - Rupesh Raj Karn, Kashif Nawaz, Ibrahim Abe M. Elfadel:
Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation. 1-6 - Yi Chen, Jie Lou, Christian Lanius, Florian Freye, Johnson Loh, Tobias Gemmeke:
An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access. 1-6 - Aishwarya Gupta, N. S. Aswathy, Hemangee K. Kapoor:
Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories. 1-6 - Ankit Sirohi, Jawar Singh:
A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact. 1-6 - Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. 1-6 - Kais Belwafi, Hamdan Alshamsi, Ashfaq Ahmed, Abdulhadi Shoufan:
Zero-Trust Communication between Chips. 1-5 - Esha Sarkar, Constantine Doumanidis, Michail Maniatakos:
TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis. 1-6 - Jingbo Jiang, Xizi Chen, Chi-Ying Tsui:
Accelerating Large Kernel Convolutions with Nested Winograd Transformation. 1-6 - Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf:
FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. 1-6 - Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang:
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. 1-6 - Deepraj Soni, Mohammed Nabeel, Ramesh Karri, Michail Maniatakos:
Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility. 1-6 - Anjum Riaz, Gaurav Kumar, Pardeep Kumar, Yamuna Prasad, Satyadev Ahlawat:
On Protecting IJTAG using an Inherently Secure SIB. 1-6 - Walaa Amer, Mariam Rakka, Rachid Karami, Minjun Seo, Mazen A. R. Saghir, Rouwaida Kanj, Fadi J. Kurdahi:
Hardware Implementation and Evaluation of an Information Processing Factory. 1-6 - Mouli Venkata Prakash Pittala, Aditya Kalyani, Nagaveni S:
Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V. 1-6 - Can Ayduman, Emre Koçer, Selim Kirbiyik, Ahmet Can Mert, Erkay Savas:
Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption. 1-7 - Siyi Wang, Anupam Chattopadhyay:
Reducing Depth of Quantum Adder using Ling Structure. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 23:24 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
