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2020 – today
- 2024
[j26]Sumit Diware
, Koteswararao Chilakala, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks. IEEE Access 12: 47469-47482 (2024)- [c53]Sumit Diware, Mohammad Amin Yaldagard, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks. AICAS 2024: 393-397 - [c52]Muhammad Ali Siddiqi, David Vrijenhoek, Lennart P. L. Landsmeer, Job van der Kleij, Anteneh Gebregiorgis, Vincenzo Romano, Rajendra Bishnoi, Said Hamdioui, Christos Strydis:
A Lightweight Architecture for Real-Time Neuronal-Spike Classification. CF 2024 - [i3]Muhammad Ali Siddiqi, Jan Andrés Galvan Hernández, Anteneh Gebregiorgis, Rajendra Bishnoi, Christos Strydis, Said Hamdioui, Mottaqiallah Taouil:
Memristor-Based Lightweight Encryption. CoRR abs/2404.00125 (2024) - 2023
- [j25]Sumit Diware, Sudeshna Dash, Anteneh Gebregiorgis, Rajiv V. Joshi, Christos Strydis, Said Hamdioui, Rajendra Bishnoi:
Severity-Based Hierarchical ECG Classification Using Neural Networks. IEEE Trans. Biomed. Circuits Syst. 17(1): 77-91 (2023) - [j24]Sumit Diware, Abhairaj Singh, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks. IEEE Trans. Emerg. Top. Comput. Intell. 7(1): 164-177 (2023) - [c51]Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Mapping-aware Biased Training for Accurate Memristor-based Neural Networks. AICAS 2023: 1-5 - [c50]Abhairaj Singh, Rajendra Bishnoi, Ali Kaichouhi, Sumit Diware, Rajiv V. Joshi, Said Hamdioui:
A 115.1 TOPS/W, 12.1 TOPS/mm2 Computation-in-Memory using Ring-Oscillator based ADC for Edge AI. AICAS 2023: 1-5 - [c49]Mohammad Amin Yaldagard, Sumit Diware, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture. AICAS 2023: 1-5 - [c48]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE 2023: 1-6 - [c47]Muhammad Ali Siddiqi, Jan Andrés Galvan Hernández, Anteneh Gebreziorgis, Rajendra Bishnoi, Christos Strydis, Said Hamdioui, Mottaqiallah Taouil:
Memristor-Based Lightweight Encryption. DSD 2023: 634-641 - [c46]Manil Dev Gomony, Anteneh Gebregiorgis, Moritz Fieback, Marc Geilen, Sander Stuijk, Jan Richter-Brockmann, Rajendra Bishnoi, Sven Argo, Lara Arche Andradas, Tim Güneysu, Mottaqiallah Taouil, Henk Corporaal, Said Hamdioui:
Dependability of Future Edge-AI Processors: Pandora's Box. ETS 2023: 1-6 - [c45]Rajendra Bishnoi, Sumit Diware, Anteneh Gebregiorgis, Simon Thomann, Sara Mannaa, Bastien Deveautour, Cédric Marchand, Alberto Bosio, Damien Deleruyelle, Ian O'Connor, Hussam Amrouch, Said Hamdioui:
Energy-efficient Computation-In-Memory Architecture using Emerging Technologies. ICM 2023: 325-334 - [c44]Hassen Aziza, Cristian Zambelli, Said Hamdioui, Sumit Diware, Rajendra Bishnoi, Anteneh Gebregiorgis:
On the Reliability of RRAM-Based Neural Networks. VLSI-SoC 2023: 1-8 - [i2]Muhammad Ali Siddiqi, David Vrijenhoek, Lennart P. L. Landsmeer, Job van der Kleij, Anteneh Gebregiorgis, Vincenzo Romano, Rajendra Bishnoi, Said Hamdioui, Christos Strydis:
A Lightweight Architecture for Real-Time Neuronal-Spike Classification. CoRR abs/2311.04808 (2023) - 2022
- [j23]Mahta Mayahinia, Abhairaj Singh, Christopher Bengel, Stefan Wiefels, Muath Abu Lebdeh, Stephan Menzel, Dirk J. Wouters, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui:
A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs. ACM J. Emerg. Technol. Comput. Syst. 18(2): 32:1-32:25 (2022) - [j22]Moritz Fieback, Guilherme Cardoso Medeiros, Lizhou Wu, Hassen Aziza, Rajendra Bishnoi, Mottaqiallah Taouil, Said Hamdioui:
Defects, Fault Modeling, and Test Development Framework for RRAMs. ACM J. Emerg. Technol. Comput. Syst. 18(3): 52:1-52:26 (2022) - [j21]Anteneh Gebregiorgis, Hoang Anh Du Nguyen, Jintao Yu, Rajendra Bishnoi, Mottaqiallah Taouil, Francky Catthoor, Said Hamdioui:
A Survey on Memory-centric Computer Architectures. ACM J. Emerg. Technol. Comput. Syst. 18(4): 79:1-79:50 (2022) - [j20]Christopher Bengel, Johannes Mohr, Stefan Wiefels, Abhairaj Singh, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Rainer Waser, Dirk J. Wouters, Stephan Menzel:
Reliability aspects of binary vector-matrix-multiplications using ReRAM devices. Neuromorph. Comput. Eng. 2(3): 34001 (2022) - [c43]Abhairaj Singh, Mahdi Zahedi, Taha Shahroodi, Mohit Gupta, Anteneh Gebregiorgis, Manu Komalan, Rajiv V. Joshi, Francky Catthoor, Rajendra Bishnoi, Said Hamdioui:
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. AICAS 2022: 451-454 - [c42]Abhairaj Singh, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui:
Referencing-in-Array Scheme for RRAM-based CIM Architecture. DATE 2022: 1413-1418 - [c41]Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui:
Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. ITC 2022: 400-409 - [c40]Anteneh Gebregiorgis, Abhairaj Singh, Sumit Diware, Rajendra Bishnoi, Said Hamdioui:
Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs. VLSI-SoC 2022: 1-6 - [i1]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
CONVOLVE: Smart and seamless design of smart edge processors. CoRR abs/2212.00873 (2022) - 2021
- [j19]Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori:
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE 109(2): 149-169 (2021) - [j18]Abhairaj Singh, Muath Abu Lebdeh, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui:
SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1917-1930 (2021) - [c39]Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture. AICAS 2021: 1-4 - [c38]Abhairaj Singh, Sumit Diware, Anteneh Gebregiorgis, Rajendra Bishnoi, Francky Catthoor, Rajiv V. Joshi, Said Hamdioui:
Low-Power Memristor-Based Computing for Edge-AI Applications. ISCAS 2021: 1-5 - 2020
- [j17]Farhan Rasheed, Michael Hefenbrock, Rajendra Bishnoi, Michael Beigl, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
Crossover-aware Placement and Routing for Inkjet Printed Circuits. ACM J. Emerg. Technol. Comput. Syst. 16(2): 19:1-19:22 (2020) - [j16]Nour Sayed, Rajendra Bishnoi, Mehdi B. Tahoori:
Approximate Spintronic Memories. ACM J. Emerg. Technol. Comput. Syst. 16(4): 43:1-43:22 (2020) - [j15]Samir Ben Dodo, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 263-272 (2020) - [j14]Ahmet Turan Erozan, Guan Ying Wang, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1485-1495 (2020) - [j13]Ahmet Turan Erozan, Dennis D. Weller, Farhan Rasheed, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1496-1504 (2020) - [c37]Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories. ASP-DAC 2020: 393-400 - [c36]Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat:
A Universal Spintronic Technology based on Multifunctional Standardized Stack. DATE 2020: 394-399 - [c35]Sarath Mohanachandran Nair, Rajendra Bishnoi, Arunkumar Vijayan, Mehdi Baradaran Tahoori:
Dynamic Faults based Hardware Trojan Design in STT-MRAM. DATE 2020: 933-938 - [c34]Moritz Fieback, Surya Nagarajan, Rajendra Bishnoi, Mehdi B. Tahoori, Mottaqiallah Taouil, Said Hamdioui:
Testing Scouting Logic-Based Computation-in-Memory Architectures. ETS 2020: 1-6 - [c33]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi B. Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor:
Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects. IRPS 2020: 1-5 - [c32]Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui:
Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. VTS 2020: 1-10 - [c31]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Mitigating Read Failures in STT-MRAM. VTS 2020: 1-6
2010 – 2019
- 2019
- [j12]Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 439-452 (2019) - [j11]Nour Sayed, Longfei Mao, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design. ACM Trans. Design Autom. Electr. Syst. 24(4): 41:1-41:25 (2019) - [j10]Nour Sayed, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1329-1342 (2019) - [j9]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1697-1710 (2019) - [j8]Samir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori:
A Spintronics Memory PUF for Resilience Against Cloning Counterfeit. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2511-2522 (2019) - [c30]Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Reliable in-memory neuromorphic computing using spintronics. ASP-DAC 2019: 230-236 - [c29]Farhan Rasheed, Michael Hefenbrock, Rajendra Bishnoi, Michael Beigl, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
Predictive Modeling and Design Automation of Inorganic Printed Electronics. DATE 2019: 30-35 - [c28]Ahmet Turan Erozan, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning. DATE 2019: 1361-1366 - [c27]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Hayk T. Grigoryan, Grigor Tshagharyan:
Variation-aware Fault Modeling and Test Generation for STT-MRAM. IOLTS 2019: 80-83 - [c26]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor:
Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects. IRPS 2019: 1-6 - 2018
- [j7]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori:
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1396-1407 (2018) - [j6]Ahmet Turan Erozan, Gabriel Cadilha Marques, Mohammad Saber Golanbari, Rajendra Bishnoi, Simone Dehm, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2935-2946 (2018) - [c25]Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM. ASP-DAC 2018: 203-208 - [c24]Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Spintronic normally-off heterogeneous system-on-chip design. DATE 2018: 113-118 - [c23]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Parametric failure modeling and yield analysis for STT-MRAM. DATE 2018: 265-268 - [c22]Nour Sayed, Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
A cross-layer adaptive approach for performance and power optimization in STT-MRAM. DATE 2018: 791-796 - [c21]Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat:
Using multifunctional standardized stack as universal spintronic technology for IoT. DATE 2018: 931-936 - [c20]Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Multi-bit non-volatile spintronic flip-flop. DATE 2018: 1229-1234 - [c19]Mohammad Saber Golanbari, Saman Kiamehr, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Reliable memory PUF design for low-power applications. ISQED 2018: 207-213 - [c18]Ahmet Turan Erozan, Mohammad Saber Golanbari, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
Design and evaluation of physical unclonable function for inorganic printed electronics. ISQED 2018: 419-424 - [c17]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian:
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. ITC 2018: 1-10 - [c16]Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications. ITC 2018: 1-10 - 2017
- [b1]Rajendra Bishnoi:
Reliable Low-Power High Performance Spintronic Memories. Karlsruhe University, Germany, 2017 - [j5]Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1421-1432 (2017) - [c15]Nour Sayed, Mojtaba Ebrahimi, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Opportunistic write for fast and reliable STT-MRAM. DATE 2017: 554-559 - [c14]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori:
VAET-STT: A variation aware estimator tool for STT-MRAM based memories. DATE 2017: 1456-1461 - [c13]Nour Sayed, Fabian Oboril, Azadeh Shirvanian, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Exploiting STT-MRAM for approximate computing. ETS 2017: 1-6 - [c12]Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Baradaran Tahoori, Adwait Jog, Jeffrey S. Vetter:
Architecting SOT-RAM Based GPU Register File. ISVLSI 2017: 38-44 - [c11]Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat:
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. ISVLSI 2017: 344-349 - [c10]Nour Sayed, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache. VTS 2017: 1-6 - 2016
- [j4]Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Layout-Based Modeling and Mitigation of Multiple Event Transients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 367-379 (2016) - [j3]Guillaume Prenat, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Nathalie Lamard, Olivier Boulle, Kevin Garello, Juergen Langer, Berthold Ocker, Marie Claire Cyrille, Pietro Gambardella, Mehdi Baradaran Tahoori, Gilles Gaudin:
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. IEEE Trans. Multi Scale Comput. Syst. 2(1): 49-60 (2016) - [j2]Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Self-Timed Read and Write Operations in STT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1783-1793 (2016) - [c9]Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing. ASP-DAC 2016: 769-774 - [c8]Anteneh Gebregiorgis, Saman Kiamehr, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing. DATE 2016: 205-210 - [c7]Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Fault Tolerant Non-Volatile spintronic flip-flop. DATE 2016: 261-264 - [c6]Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices. ACM Great Lakes Symposium on VLSI 2016: 409-414 - [c5]Fabian Oboril, Fazal Hameed, Rajendra Bishnoi, Ali Ahari, Helia Naeimi, Mehdi Baradaran Tahoori:
Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches. ISLPED 2016: 236-241 - 2015
- [j1]Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 367-380 (2015) - 2014
- [c4]Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori:
Architectural aspects in design and analysis of SOT-based memories. ASP-DAC 2014: 700-707 - [c3]Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori:
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM. DATE 2014: 1-6 - [c2]Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Avoiding unnecessary write operations in STT-MRAM for low power implementation. ISQED 2014: 548-553 - [c1]Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori:
Read disturb fault detection in STT-MRAM. ITC 2014: 1-7
Coauthor Index
Mehdi Baradaran Tahoori
aka: Mehdi B. Tahoori
aka: Mehdi B. Tahoori
[j19] [j17] [j16] [j15] [j14] [j13] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [j12] [j11] [j10] [j9] [j8] [c30] [c29] [c28] [c27] [c26] [j7] [j6] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [j5] [c15] [c14] [c13] [c12] [c11] [c10] [j4] [j3] [j2] [c9] [c8] [c7] [c6] [c5] [j1] [c4] [c3] [c2] [c1]
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