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2020 – today
- 2024
[c108]Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Joseph Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikaël Cassé, Philippe Galy:
LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching. NewCAS 2024: 65-69- [c107]Oumayma Belkhadra, Gilles Montoriol, Emmanuel Pistone, Hugo Vallee, Florent Cilici, Manuel J. Barragán, Salvador Mir, Sylvain Bourdel:
An Integrated Miniaturized VNA for On-Chip PA Mismatch Measurement. NewCAS 2024: 228-232 - 2023
- [c106]Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán:
A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. ISCAS 2023: 1-5 - [c105]Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán:
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. LATS 2023: 1-2 - [c104]Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán:
Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. LATS 2023: 1-2 - [c103]Ankush Mamgain, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Jai Narayan Tripathi:
A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA. NEWCAS 2023: 1-5 - [c102]Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy:
Noise modeling using look-up tables and DC measurements for cryogenic applications. VLSI-SoC 2023: 1-6 - 2022
- [c101]Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi
, Manuel J. Barragán:
On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. ATS 2022: 43-48 - [c100]William R. Eisenstadt, Mark Roos, Devin Morris, José Luis González-Jiménez, Christopery Mounet, Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquière:
Special Session on RF/5G Test. ETS 2022: 1-9 - [c99]Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán:
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. VLSI-SoC 2022: 1-6 - [c98]Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS 2022: 1 - 2021
- [c97]Ankush Mamgain, Manuel J. Barragán, Salvador Mir:
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. ETS 2021: 1-6 - 2020
- [j33]Ahcène Bounceur, Salvador Mir, Reinhardt Euler, Kamel Beznia:
Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5): 966-976 (2020) - [c96]Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir:
On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter. ETS 2020: 1-2 - [c95]Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir:
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS 2020: 1-4 - [c94]Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir:
Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique. NEWCAS 2020: 295-298
2010 – 2019
- 2019
- [j32]Guillaume Renaud, Mamadou Diallo, Manuel J. Barragán, Salvador Mir:
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 281-293 (2019) - [c93]Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, Salvador Mir:
On the use of causal feature selection in the context of machine-learning indirect test. DATE 2019: 276-279 - [c92]Hani Malloug, Manuel J. Barragán, Salvador Mir:
A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. ETS 2019: 1-6 - [c91]Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel, Gildas Léger:
Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. ISCAS 2019: 1-5 - [c90]Florent Cilici, Gildas Léger, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel:
Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. SMACD 2019: 17-20 - [c89]Renato S. Feitoza, Manuel J. Barragán, Salvador Mir:
Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. VLSI-SoC 2019: 263-268 - 2018
- [j31]Hani Malloug, Manuel J. Barragán, Salvador Mir:
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. J. Electron. Test. 34(3): 263-279 (2018) - [c88]Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel:
Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. ETS 2018: 1-6 - [c87]Renato S. Feitoza, Manuel J. Barragán, Salvador Mir, Daniel Dzahini:
Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. IOLTS 2018: 29-34 - 2017
- [c86]Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Hervé Le Gall:
Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. ETS 2017: 1-6 - [c85]Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir:
Mixed-signal BIST computation offloading using IEEE 1687. ETS 2017: 1-2 - [c84]Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragán, Salvador Mir:
Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. VTS 2017: 1-6 - 2016
- [j30]Manuel J. Barragán, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test 33(6): 46-54 (2016) - [j29]Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet:
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. 32(4): 407-421 (2016) - [j28]Manuel J. Barragán, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1876-1888 (2016) - [c83]Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld:
Built-in test of millimeter-Wave circuits based on non-intrusive sensors. DATE 2016: 505-510 - [c82]Cédric Pastorelli, Pascal Mellot, Salvador Mir, Cédric Tubert:
ADC Techniques for Optimized Conversion Time in CMOS Image Sensors. IMSE 2016: 1-6 - [c81]Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragán, Salvador Mir:
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS 2016: 1-6 - 2015
- [j27]Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld:
Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors. J. Electron. Test. 31(4): 381-394 (2015) - [j26]Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet:
Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2391-2400 (2015) - [j25]Kamel Beznia, Ahcène Bounceur, Reinhardt Euler, Salvador Mir:
A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters. ACM Trans. Design Autom. Electr. Syst. 20(2): 31:1-31:22 (2015) - [c80]Hervé Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu:
High frequency jitter estimator for SoCs. ETS 2015: 1-6 - [c79]Athanasios Dimakos, Martin Andraud, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Salvador Mir:
Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors. ISVLSI 2015: 627 - [c78]Haralampos-G. D. Stratigopoulos, Manuel J. Barragán, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC 2015: 1-7 - [c77]Richun Fei, Jocelyn Moreau, Salvador Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou:
Horizontal-FPN fault coverage improvement in production test of CMOS imagers. VTS 2015: 1-6 - 2014
- [c76]Guillaume Renaud, Manuel J. Barragán, Salvador Mir, Marc Sabut:
On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. ATS 2014: 212-217 - [c75]Ayssar Serhan, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Low-cost EVM built-in test of RF transceivers. IDT 2014: 51-54 - [c74]Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos:
Solutions for the self-adaptation of communicating systems in operation. IOLTS 2014: 234-239 - [c73]Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo:
Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. MWSCAS 2014: 1081-1084 - [c72]Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán:
Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. VLSI-SoC 2014: 1-6 - [c71]Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán:
Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST. VLSI-SoC (Selected Papers) 2014: 129-148 - 2013
- [j24]Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret:
Reduced-Code Linearity Testing of Pipeline ADCs. IEEE Des. Test 30(6): 80-88 (2013) - [c70]Ke Huang, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Salvador Mir, Ahcène Bounceur:
Multivariate statistical techniques for analog parametric test metrics estimation. DTIS 2013: 6-11 - [c69]Kamel Beznia, Ahcène Bounceur, Salvador Mir, Reinhardt Euler:
Statistical modelling of analog circuits for test metrics computation. DTIS 2013: 25-29 - [c68]Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir:
Efficient minimization of test frequencies for linear analog circuits. ETS 2013: 1 - [c67]Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir:
True non-intrusive sensors for RF built-in test. ITC 2013: 1-10 - [c66]Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Fault modeling and diagnosis for nanometric analog circuits. ITC 2013: 1-10 - [c65]Richun Fei, Jocelyn Moreau, Salvador Mir:
BIST of interconnection lines in the pixel matrix of CMOS imagers. IWASI 2013: 174-177 - [c64]Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir:
New techniques for selecting test frequencies for linear analog circuits. VLSI-SoC 2013: 90-95 - [c63]Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Salvador Mir, Yann Kieffer:
Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods. VLSI-SoC (Selected Papers) 2013: 188-207 - [c62]Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet:
Defect-oriented non-intrusive RF test using on-chip temperature sensors. VTS 2013: 1-6 - [c61]Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret:
Reduced code linearity testing of pipeline adcs in the presence of noise. VTS 2013: 1-6 - 2012
- [j23]Haralampos-G. D. Stratigopoulos, Salvador Mir:
Adaptive Alternate Analog Test. IEEE Des. Test Comput. 29(4): 71-79 (2012) - [j22]Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir, Camelia Hora, Yizi Xing, Bram Kruseman:
Diagnosis of Local Spot Defects in Analog Circuits. IEEE Trans. Instrum. Meas. 61(10): 2701-2712 (2012) - [c60]Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet:
Testing RF circuits with true non-intrusive built-in sensors. DATE 2012: 1090-1095 - [c59]Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Christophe Forel:
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. ETS 2012: 1-6 - [c58]Kamel Beznia, Ahcène Bounceur, Louay Abdallah, Ke Huang, Salvador Mir, Reinhardt Euler:
Accurate estimation of analog test metrics with extreme circuits. ICECS 2012: 272-275 - [c57]Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma:
Experiences with non-intrusive sensors for RF built-in test. ITC 2012: 1-8 - [c56]Nourredine Akkouche, Salvador Mir, Emmanuel Simeu, Mustapha Slamani:
Analog/RF test ordering in the early stages of production testing. VTS 2012: 25-30 - [e2]Salvador Mir, Chi-Ying Tsui, Ricardo Reis, Oliver C. S. Choy:
VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers. IFIP Advances in Information and Communication Technology 379, Springer 2012, ISBN 978-3-642-32769-8 [contents] - 2011
- [j21]Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma:
RF Front-End Test Using Built-in Sensors. IEEE Des. Test Comput. 28(6): 76-84 (2011) - [j20]Ahcène Bounceur, Salvador Mir, Haralampos-G. D. Stratigopoulos:
Estimation of Analog Parametric Test Metrics Using Copulas. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1400-1410 (2011) - [c55]Alexios Spyronasios, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir:
On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study. Asian Test Symposium 2011: 365-370 - [c54]Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Implicit test of high-speed analog circuits using non-intrusive sensors. ECCTD 2011: 652 - 2010
- [j19]Fabio Cenni, Jeremie Cazalbou, Salvador Mir, Libor Rufer:
Design of a SAW-based chemical sensor with its microelectronics front-end interface. Microelectron. J. 41(11): 723-732 (2010) - [c53]Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation. Asian Test Symposium 2010: 295-298 - [c52]Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Fault diagnosis of analog circuits based on machine learning. DATE 2010: 1761-1766 - [c51]Gustavo Pamplona Rehder, Salvador Mir, Libor Rufer, Emmanuel Simeu, Hoang Nam Nguyen:
Low Frequency Test for RF MEMS Switches. DELTA 2010: 350-354 - [c50]Louay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir:
Sensors for built-in alternate RF test. ETS 2010: 49-54 - [c49]Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev:
Defect filter for alternate RF test. ETS 2010: 265-270 - [c48]Haralampos-G. D. Stratigopoulos, Salvador Mir:
Analog test metrics estimates with PPM accuracy. ICCAD 2010: 241-247 - [c47]Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni:
Adaptive Logical Control of RF LNA Performances for Efficient Energy Consumption. VLSI-SoC (Selected Papers) 2010: 43-68 - [c46]Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni:
Adaptive logical control of RF LNA performances for efficient energy consumption. VLSI-SoC 2010: 161-166 - [c45]Salvador Mir, Haralampos-G. D. Stratigopoulos, Ahcène Bounceur:
Density estimation for analog/RF test problem solving. VTS 2010: 41 - [c44]Nourredine Akkouche, Salvador Mir, Emmanuel Simeu:
Ordering of analog specification tests based on parametric defect level estimation. VTS 2010: 301-306
2000 – 2009
- 2009
- [j18]Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur, Emmanuel Simeu:
Pseudorandom BIST for test and characterization of linear and nonlinear MEMS. Microelectron. J. 40(7): 1054-1061 (2009) - [j17]Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur:
Evaluation of Analog/RF Test Measurements at the Design Stage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 582-590 (2009) - [c43]Haralampos-G. D. Stratigopoulos, Salvador Mir, Yiorgos Makris:
Enrichment of limited training sets in machine-learning-based analog/RF test. DATE 2009: 1668-1673 - [c42]Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev:
Defect Filter for Alternate RF Test. ETS 2009: 101-106 - [c41]Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study. ICCD 2009: 78-83 - [c40]Rafik Khereddine, Emmanuel Simeu, Salvador Mir:
Parameter identification of RF transceiver blocks using regressive models. PDeS 2009: 67-72 - [c39]Livier Lizarraga, Salvador Mir, Gilles Sicard:
Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors. VTS 2009: 189-194 - 2008
- [j16]Emmanuel Simeu, Hoang Nam Nguyen, Philippe Cauvet, Salvador Mir, Libor Rufer, Rafik Khereddine:
Using Signal Envelope Detection for Online and Offline RF MEMS Switch Testing. VLSI Design 2008: 294014:1-294014:10 (2008) - [c38]Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir:
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. DATE 2008: 68-73 - 2007
- [j15]Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez:
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing. J. Electron. Test. 23(6): 471-484 (2007) - [c37]Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu:
Test Education in the Global Economy. ATS 2007: 53 - [c36]Livier Lizarraga, Salvador Mir, Gilles Sicard:
Evaluation of a BIST Technique for CMOS Imagers. ATS 2007: 378-383 - [c35]Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro:
Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. DATE 2007: 731-736 - [c34]Emmanuel Simeu, Salvador Mir, R. Kherreddine, Hoang Nam Nguyen:
Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. IOLTS 2007: 237-243 - [c33]Luís Rolíndez, Salvador Mir, Jean-Louis Carbonéro, Dimitri Goguet, Nabil Chouba:
A stereo audio Σ∑ ADC architecture with embedded SNDR self-test. ITC 2007: 1-10 - [e1]Giovanni De Micheli, Salvador Mir, Ricardo Reis:
VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. IFIP 249, Springer 2007, ISBN 978-0-387-74908-2 [contents] - 2006
- [j14]Salvador Mir, Kwang-Ting (Tim) Cheng, Andrew Richardson:
Guest Editorial. J. Electron. Test. 22(4-6): 311 (2006) - [j13]Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro:
A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting. J. Electron. Test. 22(4-6): 325-335 (2006) - [j12]Salvador Mir, Libor Rufer, Achraf Dhayni:
Built-in-self-test techniques for MEMS. Microelectron. J. 37(12): 1591-1597 (2006) - [c32]Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur:
Pseudorandom functional BIST for linear and nonlinear MEMS. DATE 2006: 664-669 - [c31]Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu:
CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization. VLSI-SoC (Selected Papers) 2006: 281-300 - [c30]Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu:
CAT platform for analogue and mixed-signal test evaluation and optimization. VLSI-SoC 2006: 320-325 - [c29]Livier Lizarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur:
Study of a BIST Technique for CMOS Active Pixel Sensors. VLSI-SoC 2006: 326-331 - [c28]Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro:
A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. VTS 2006: 314-319 - 2005
- [j11]Libor Rufer, Salvador Mir, Emmanuel Simeu, C. Domingues:
On-Chip Pseudorandom MEMS Testing. J. Electron. Test. 21(3): 233-241 (2005) - [j10]Bozena Kaminska, Stephen K. Sunter, Salvador Mir:
Analog and mixed signal test techniques for SOC development. Microelectron. J. 36(12): 1063 (2005) - [j9]Guillaume Prenat, Salvador Mir, Diego Vázquez, Luís Rolíndez:
A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. Microelectron. J. 36(12): 1080-1090 (2005) - [c27]Rabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir:
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. DATE 2005: 170-171 - [c26]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir:
A built-in IDDQ testing circuit. ESSCIRC 2005: 471-474 - [c25]Achraf Dhayni, Salvador Mir, Libor Rufer:
Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities. ETS 2005: 82-87 - [c24]Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur:
On-chip Pseudorandom Testing for Linear and Nonlinear MEMS. VLSI-SoC 2005: 245-266 - 2004
- [c23]Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur:
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. DATE 2004: 706-707 - [c22]Achraf Dhayni, Salvador Mir, Libor Rufer:
Mems built-in-self-test using MLS. ETS 2004: 66-71 - [c21]Salvador Mir, Benoît Charlot, Libor Rufer, Bernard Courtois:
On-chip testing of embedded silicon transducers. SoCC 2004: 13-18 - [c20]Salvador Mir, Libor Rufer, Bernard Courtois:
On-chip testing of embedded transducers. VLSI Design 2004: 463- - 2003
- [j8]Cosmin Roman, Salvador Mir, Benoît Charlot:
Building an analogue fault simulation tool and its application to MEMS. Microelectron. J. 34(10): 897-906 (2003) - [c19]Salvador Mir, Luís Rolíndez, Christian Domigues, Libor Rufer:
An implementation of memory-based on-chip analogue test signal generation. ASP-DAC 2003: 663-668 - [c18]Mohammad A. Naal, Emmanuel Simeu, Salvador Mir:
On-Line Testable Decimation Filter Design for AMS Systems. IOLTS 2003: 83-88 - 2002
- [c17]Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim:
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? VTS 2002: 449-450 - 2001
- [j7]Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois:
Generation of Electrically Induced Stimuli for MEMS Self-Test. J. Electron. Test. 17(6): 459-470 (2001) - [c16]Bernard Courtois, Salvador Mir, Benoît Charlot, Marcelo Lubaszewski:
An Analog-based Approach for MEMS Testing. LATW 2001: 200-203 - [c15]Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois:
Electrically Induced Stimuli For MEMS Self-Test. VTS 2001: 210-217 - 2000
- [j6]Salvador Mir, Benoît Charlot, Bernard Courtois:
Extending Fault-Based Testing to Microelectromechanical Systems. J. Electron. Test. 16(3): 279-288 (2000) - [j5]Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois:
Design of self-checking fully differential circuits and boards. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 113-128 (2000) - [c14]Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz:
Towards design and validation of mixed-technology SOCs. ACM Great Lakes Symposium on VLSI 2000: 29-33
1990 – 1999
- 1999
- [j4]Salvador Mir, Benoît Charlot:
On the Integration of Design and Test for Chips Embedding MEMS. IEEE Des. Test Comput. 16(4): 28-38 (1999) - [c13]Salvador Mir, Benoît Charlot, Bernard Courtois:
Extending fault-based testing to microelectromechanical systems. ETW 1999: 64-68 - [c12]Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois:
Fault modeling of suspended thermal MEMS. ITC 1999: 319-328 - [c11]Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner:
Design and Test of MEMs. VLSI Design 1999: 270- - 1998
- [c10]Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas:
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. DATE 1998: 810-814 - [c9]A. Castillejo, D. Veychard, Salvador Mir, Jean-Michel Karam, Bernard Courtois:
Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems. ITC 1998: 541-550 - [c8]Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand:
A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. SBCCI 1998: 175-178 - 1997
- [c7]Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas:
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC 1997: 281-286 - 1996
- [j3]Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. J. Electron. Test. 9(1-2): 43-57 (1996) - [j2]Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Unified built-in self-test for fully differential analog circuits. J. Electron. Test. 9(1-2): 135-151 (1996) - [c6]Salvador Mir, Bernard Courtois, Marcelo Lubaszewski, Vladimir Kolarik:
Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits. ED&TC 1996: 254-258 - [c5]Marcelo Lubaszewski, Salvador Mir, Leandro Pulz:
ABILBO: Analog BuILt-in Block Observer. ICCAD 1996: 600-603 - [c4]Fabrizio Francesconi, Valentino Liberali, Marcelo Lubaszewski, Salvador Mir:
Design of high-performance band-pass sigma-delta modulator with concurrent error detection. ICECS 1996: 1202-1205 - 1995
- [j1]Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Analog checkers with absolute and relative tolerances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 607-612 (1995) - [c3]Marcelo Lubaszewski, Vladimir Kolarik, Salvador Mir, C. Nielsen, Bernard Courtois:
Mixed-signal circuits and boards for high safety applications. ED&TC 1995: 34-41 - 1994
- [c2]Salvador Mir, Nick Filer:
Re-engineering hardware specifications by exploiting design semantics. EURO-DAC 1994: 336-341 - [c1]Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois:
Built-in self-test and fault diagnosis of fully differential analogue circuits. ICCAD 1994: 486-490
Coauthor Index
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