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ORCIDJournal of Electronic Testing, Volume 32
Volume 32, Number 1, February 2016
- Vishwani D. Agrawal:
Editorial. 1-2 - New Editors - 2016. 3-5
- 2015 JETTA Reviewers. 7-8
- Test Technology Newsletter. 9-10
- Yuanqing Li, Haibin Wang, Lixiang Li, Li Chen
, Rui Liu, Mo Chen:
A Built-in Single Event Upsets Detector for Sequential Cells. 11-20 - Karine Coulié-Castellani, Wenceslas Rahajandraibe, Gilles Micolau, Hassen Aziza, Jean-Michel Portal:
Optimization of a Particles Detection Chain Based on a VCO Structure. 21-30 - Cong Hu, Zhi Li, Chuan-pei Xu, Mengyi Jia:
Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks. 31-42 - Davide Ferraretto, Graziano Pravadelli:
Simulation-based Fault Injection with QEMU for Speeding-up Dependability Analysis of Embedded Software. 43-57 - Haiying Yuan, Kun Guo, Xun Sun, Zijian Ju:
A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding. 59-68 - Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATE. 69-82 - Xiaofeng Tang, Aiqiang Xu:
Practical Analog Circuit Diagnosis Based on Fault Features with Minimum Ambiguities. 83-95 - Haibin Wang, Mulong Li, Xixi Dai, Shuting Shi, Li Chen, Gang Guo:
Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits. 97-103 - Sezer Gören, Cemil Cem Gürsoy, Abdullah Yildiz:
Erratum to: Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection. 105-106
Volume 32, Number 2, April 2016
- Vishwani D. Agrawal:
Editorial. 107-108 - Test Technology Newsletter. 109-110
- Kun-Lun Luo, Ming-Hsueh Wu, Chun-Lung Hsu, Chen-An Chen:
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. 111-123 - Zissis Poulos, Andreas G. Veneris:
Exemplar-based Failure Triage for Regression Design Debugging. 125-136 - Yuanqing Li, Lixiang Li, Yuan Ma, Li Chen, Rui Liu, Haibin Wang, Qiong Wu, Michael Newton, Mo Chen:
A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets. 137-145 - Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda:
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. 147-161 - João Guilherme Mourão Melo, Frank Sill Torres:
Exploration of Noise Impact on Integrated Bulk Current Sensors. 163-173 - A. N. Nagamani, S. Ashwin, B. Abhishek, Vinod Kumar Agrawal:
An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits. 175-196 - Yavuz Can, Hassen Kassim, Georg Fischer:
New Boolean Equation for Orthogonalizing of Disjunctive Normal Form based on the Method of Orthogonalizing Difference-Building. 197-208 - Baohu Li, Vishwani D. Agrawal:
Applications of Mixed-Signal Technology in Digital Testing. 209-225 - Hieu Nguyen, Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Martin Margala:
A CMOS Ripple Detector for Voltage Regulator Testing. 227-233 - Qian Lin, Qian-Fu Cheng, Junjie Gu, Yuanyuan Zhu, Chao Chen, Haipeng Fu:
Design and Temperature Reliability Testing for A 0.6-2.14GHz Broadband Power Amplifier. 235-240
Volume 32, Number 3, June 2016
- Vishwani D. Agrawal:
Editorial. 241-242 - Test Technology Newsletter. 243-244
- Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin:
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. 245-255 - Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. 257-271 - Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros:
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. 273-289 - Mohsen Raji, Behnam Ghavami:
A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits. 291-305 - Hector Villacorta, Jaume Segura, Víctor H. Champac:
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. 307-314 - Thiago Copetti, Guilherme Cardoso Medeiros, Leticia Bolzani Poehls, Fabian Vargas:
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time. 315-328 - Sharareh Zamanzadeh, Ali Jahanian:
Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering. 329-343 - Ehsan Saeedi, Md. Selim Hossain, Yinan Kong:
Side-Channel Information Characterisation Based on Cascade-Forward Back-Propagation Neural Network. 345-356 - Abdurrahman A. Nasr, Mohamed Z. Abdulmageed:
Automatic Feature Selection of Hardware Layout: A Step toward Robust Hardware Trojan Detection. 357-367 - Christian Streitwieser:
Real-Time Adaptive Test Algorithm Including Test Escape Estimation Method. 369-375 - R. Jothin, C. Vasanthanayaki:
High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications. 377-383 - Qingyu Chen, Haibin Wang, Li Chen, Lixiang Li, Xing Zhao, Rui Liu, Mo Chen, Xuantian Li:
An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology. 385-391 - Dongdi Zhu, Jiongjiong Mo, Shiyi Xu, Yong-Heng Shang, Zhiyu Wang, Zheng-Liang Huang, Fa-Xin Yu:
A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology. 393-397
Volume 32, Number 4, August 2016
- Vishwani D. Agrawal:
Editorial. 399 - Test Technology Newsletter. 401-403
- Gildas Léger, Carsten Wegener:
Guest Editorial: Analog, Mixed-Signal and RF Testing. 405-406 - Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet:
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. 407-421 - Yan Li, Steven Bielby, Azhar A. Chowdhury, Gordon W. Roberts:
A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O. 423-436 - Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Poras T. Balsara:
A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation. 437-445 - Friedrich Peter Leisenberger, Gregor Schatzberger:
An Efficient Contact Screening Method and its Application to High-Reliability Non-Volatile Memories. 447-458 - Wenxin Yu, Yongbo Sui, Junnian Wang:
The Faults Diagnostic Analysis for Analog Circuit Based on FA-TM-ELM. 459-465 - Cristina C. Oliveira, José Machado da Silva:
Fault Diagnosis in Highly Dependable Medical Wearable Systems. 467-479 - Qian Lin, Haipeng Fu, Feifei He, Qian-Fu Cheng:
Interconnect Reliability Analysis for Power Amplifier Based on Artificial Neural Networks. 481-489 - Gürkan Uygur, Sebastian Sattler:
A New Approach for Modeling Inconsistencies in Digital-Assisted Analog Design. 491-503
Volume 32, Number 5, October 2016
- Vishwani D. Agrawal:
Editorial. 505-506 - Test Technology Newsletter. 507-509
- Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimization of Test Wrapper for TSV Based 3D SOCs. 511-529 - Chaolong Zhang, Yigang He, Lifen Yuan, Wei He, Sheng Xiang, Zhigang Li:
A Novel Approach for Diagnosis of Analog Circuit Fault by Using GMKL-SVM and PSO. 531-540 - Fathollah Bistouni, Mohsen Jahanshahi:
Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks. 541-568 - Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah R. Awwad:
Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification. 569-586 - T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi:
Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT. 587-599 - Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato:
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. 601-609 - Jaya Dofe, Hoda Pahlevanzadeh, Qiaoyan Yu:
A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack. 611-624 - Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang:
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. 625-638 - Haiying Yuan, Zijian Ju, Xun Sun, Kun Guo, Xiuyu Wang:
Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding. 639-647 - Bing Hou, Tong Liu, Jun Liu, Junli Chen, Fa-Xin Yu, Wenbo Wang:
A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors. 649-652
Volume 32, Number 6, December 2016
- Vishwani D. Agrawal:
Editorial. 653-654 - Test Technology Newsletter. 655-657
- 2015 JETTA-TTTC Best Paper Award. 659-660
- Yiqian Cui, Junyou Shi, Zili Wang:
Analog Circuit Test Point Selection Incorporating Discretization-Based Fuzzification and Extended Fault Dictionary to Handle Component Tolerances. 661-679 - Zewen Hu, Mingqing Xiao, Lei Zhang, Shuai Liu, Yawei Ge:
Mahalanobis Distance Based Approach for Anomaly Detection of Analog Filters Using Frequency Features and Parzen Window Density Estimation. 681-693 - Qingyu Chen, Li Chen, Haibin Wang, Longsheng Wu, Yuanqing Li, Xing Zhao, Mo Chen:
Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory. 695-703 - Mohamed Hanafy, Hazem Said, Ayman M. Wahba:
New Methodology for Complete Properties Extraction from Simulation Traces Guided with Static Analysis. 705-719 - Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard:
An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. 721-733 - Harpreet Vohra, Amardeep Singh:
Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression. 735-747 - Aiwu Ruan, Haiyang Huang, Jingwu Wang, Yifan Zhao:
A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs. 749-762 - Jun Liu, Yu Ping Huang, Kai Lu:
Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure. 763-767
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