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ORCIDVLSI Design, Volume 14
Volume 14, Number 1, 2002
- Bogdan J. Falkowski:
Spectral Techniques and Decision Diagrams - Guest Editorial. 1-3 - Radomir S. Stankovic, Bogdan J. Falkowski:
Spectral Transforms Calculation through Decision Diagrams. 5-12 - Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Marek A. Perkowski:
Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs. 13-21 - Radomir S. Stankovic, Jaakko Astola, Milena Stankovic, Karen O. Egiazarian:
Circuit Synthesis from Fibonacci Decision Diagrams. 23-34 - Marek A. Perkowski, Bogdan J. Falkowski, Malgorzata Chrzanowska-Jeske, Rolf Drechsler
:
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts. 35-52 - Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther:
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs. 53-64 - Radomir S. Stankovic, Milena Stankovic, Reiner Creutzburg:
Foundations for Applications of Gibbs Derivatives in Logic Design and VLSI. 65-81 - Bogdan J. Falkowski:
Spectral Testing of Digital Circuits. 83-105 - Lech Józwiak, Aleksander Slusarczyk, Marek A. Perkowski:
Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits. 107-122
Volume 14, Number 2, 2002
- Albert Y. Zomaya, Roger Karpin, Stephan Olariu:
The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms. 123-141 - Sung-Woo Hur, John Lillis:
Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. 143-154 - Chien-In Henry Chen, Mahesh Wagh:
Testability Synthesis for Jumping Carry Adders. 155-169 - Manuel Martínez, Maria José Avedillo, José M. Quintana, José Luis Huertas:
COPAS: A New Algorithm for the Partial Input Encoding Problem. 171-181 - Wei Wang, M. N. S. Swamy, M. Omair Ahmad, Yuke Wang:
A Parallel Residue-to-binary Converter for the Moduli Set {2m-1, 220m+1, 221m+1, ..., 22km+1}. 183-191 - Chua-Chin Wang, Ya-Hsin Hsueh, Shao-Ku Huang:
An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method. 193-202 - Panagiotis K. Merakos, Konstantinos Masselos, Constantinos E. Goutis:
Power Efficient Hierarchical Scheduling for DSP Transformations. 203-217 - May Huang, Raymond Kwok, Shu-park Chan:
An Empirical Algorithm for Power Analysis in Deep Submicron Electronic Designs. 219-227
Volume 14, Number 3, 2002
- Jacir Luiz Bordim, Tatsuya Hayashi, Koji Nakano:
An Algorithm Visualization Tool on the Reconfigurable Mesh. 239-248 - Kiseon Cho, Minkyu Song:
Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique. 249-258 - Chip-Hong Chang, Bogdan J. Falkowski:
Boolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix. 259-271 - Nikolaos D. Zervas, Konstantinos Masselos, Yorgos A. Karayiannis, Costas E. Goutis:
Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores. 273-286 - Sangjin Hong, Suhwan Kim, Wayne E. Stark:
Low-power Application-specific Parallel Array Multiplier Design for DSP Applications. 287-298 - Bo-Sung Kim, Jun-Dong Cho:
Maximizing Memory Data Reuse for Lower Power Motion Estimation. 299-305 - Bogdan J. Falkowski, Sudha Kannurao:
Identification of Disjoint Bi-decompositions in Boolean Functions through Walsh Spectrum. 307-313
Volume 14, Number 4, 2002
- Ashok Kumar Srivastava, D. Govindarajan:
A Fast ALU Design in CMOS for Low Voltage Operation. 315-327 - Seetharaman Ramachandran, S. Srinivasan:
A Novel, Automatic Quality Control Scheme for Real Time Image Transmission. 329-335 - Rong Lin, Stephan Olariu:
Fast Inner Product Computation on Short Buses. 337-347 - László Varga, Gábor Hosszú, Ferenc Kovács:
Design Procedure Based on VHDL Language Transformations. 349-354 - Tetsuya Kajita, Un-Ku Moon, Gabor C. Temes:
A Noise-shaping Accelerometer Interface Circuit for Two-chip Implementation. 355-361 - Eugene Grayver, Babak Daneshrad:
Word-serial Architectures for Filtering and Variable Rate Decimation. 363-372 - Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen:
Design of an Inter-plane Circuit for Clocked PLAs. 373-381 - Chua-Chin Wang, Po-Ming Lee, Chenn-Jung Huang:
Improved Design of C2PL 3-2 Compressors for Inner Product Processing. 383-388 - Chua-Chin Wang, Ya-Hsin Hsueh, Hsin-Long Wu, Chih-Feng Wu:
A Fast Dynamic 64-bit Comparator with Small Transistor Count. 389-395
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