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Malgorzata Chrzanowska-Jeske
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2020 – today
- 2024
- [c60]Abdullah Mansoor, Malgorzata Chrzanowska-Jeske:
SERS-3DPlace: Ensemble Reinforcement Learning for 3D Monolithic Placement. ISCAS 2024: 1-5 - 2022
- [c59]Abdullah Mansoor, Malgorzata Chrzanowska-Jeske:
RS3DPlace: Monolithic 3D IC placement using Reinforcement Learning and Simulated Annealing. ISCAS 2022: 394-398 - 2021
- [j15]Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske:
Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 271-275 (2021) - [c58]Satya K. Vendra, Malgorzata Chrzanowska-Jeske:
Fast Thermal Goodness Evaluation of a 3D-IC Floorplan. ISQED 2021: 367-373
2010 – 2019
- 2019
- [j14]Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 573-586 (2019) - 2018
- [c57]Satya K. Vendra, Malgorzata Chrzanowska-Jeske:
Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile. ISCAS 2018: 1-5 - 2016
- [c56]Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Buffered Interconnects in 3D IC Layout Design. SLIP 2016: 4:1-4:8 - [c55]Malgorzata Chrzanowska-Jeske, Jürgen Becker:
Tutorial 2A: 3D integration - challenges and advantages. SoCC 2016: 1-3 - [c54]Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Performance optimization and power efficiency in 3D IC with buffer insertion scheme. SoCC 2016: 229-234 - 2015
- [c53]Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Dynamic nets-to-TSVs assignment in 3D floorplanning. ISCAS 2015: 1870-1873 - 2014
- [c52]Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
3D floorplanning with nets-to-TSVs assignment. ICECS 2014: 578-581 - [c51]Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes. ICECS 2014: 774-777 - [c50]Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
Delay and power optimization with TSV-aware 3D floorplanning. ISQED 2014: 189-196 - [c49]Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
TSVs in early layout design exploration for 3D ICs. LASCAS 2014: 1-4 - 2013
- [c48]Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
TSV capacitance aware 3-D floorplanning. 3DIC 2013: 1-6 - [c47]Branimir Pejcinovic, Melinda Holtzman, Malgorzata Chrzanowska-Jeske, Phillip K. Wong:
Just because we teach it does not mean they use it: Case of programming skills. FIE 2013: 1287-1289 - [c46]Shantesh Pinge, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske:
Fast floorplanning with placement constraints. LASCAS 2013: 1-4 - 2012
- [c45]Mohammad A. Ahmed, Shantesh Pinge, Malgorzata Chrzanowska-Jeske:
Fast floorplanning for fixed-outline and nonrectangular regions. ICECS 2012: 464-467 - [c44]Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
TSV stress-aware performance and reliability analysis. ICECS 2012: 737-740 - [c43]Malgorzata Chrzanowska-Jeske, Rehman Ashraf, Rajeev K. Nain, Siva G. Narendra:
Performance analysis of CNFET based circuits in the presence of fabrication imperfections. ISCAS 2012: 1363-1366 - 2011
- [j13]Rajeev K. Nain, Malgorzata Chrzanowska-Jeske:
Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1667-1680 (2011) - 2010
- [c42]Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Yield enhancement by tube redundancy in CNFET-based circuits. ICECS 2010: 442-445 - [c41]Rajeev K. Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske:
Yield improvement of 3D ICs in the presence of defects in through signal vias. ISQED 2010: 598-605 - [c40]Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes. NANOARCH 2010: 71-76
2000 – 2009
- 2009
- [c39]Rajeev K. Nain, Malgorzata Chrzanowska-Jeske:
Placement-aware 3D Floorplanning. ISCAS 2009: 1727-1730 - 2008
- [c38]Rajeev K. Nain, Rajarshi Ray, Malgorzata Chrzanowska-Jeske:
Rectangular 3D wirelength distribution models. ICECS 2008: 109-112 - [c37]Rehman Ashraf, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Carbon nanotube circuit design choices in the presence of metallic tubes. ISCAS 2008: 177-180 - [c36]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Optimization of active circuits for substrate noise suppression. ISCAS 2008: 3418-3421 - 2007
- [j12]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Supply current spectrum estimation of digital cores at early design. IET Circuits Devices Syst. 1(3): 233-240 (2007) - [j11]Tao Wan, Malgorzata Chrzanowska-Jeske:
A novel net-degree distribution model and its application to floorplanning benchmark generation. Integr. 40(4): 420-433 (2007) - 2006
- [j10]Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 743-755 (2006) - [j9]Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Linear cofactor relationships in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1011-1023 (2006) - [c35]Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC 2006: 510-515 - [c34]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Estimation of supply current spectrum for early noise evaluation. ISCAS 2006 - 2005
- [c33]Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC 2005: 266-271 - [c32]Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang:
Substrate noise modeling in early floorplanning of MS-SOCs. ASP-DAC 2005: 819-823 - [c31]Yu Xia, Malgorzata Chrzanowska-Jeske:
Considering layout for test scheduling of core-based SoCs. ICECS 2005: 1-4 - [c30]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Modeling of substrate noise block properties for early prediction. ISCAS (3) 2005: 3015-3018 - [c29]Malgorzata Chrzanowska-Jeske, Alan Mishchenko:
Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. ISCAS (5) 2005: 4721-4724 - 2004
- [c28]Tao Wan, Malgorzata Chrzanowska-Jeske:
Generating random benchmark circuits for floorplanning. ISCAS (5) 2004: 345-348 - [c27]Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang:
Substrate noise-aware floorplanning for mixed-signal SOCs. ISCAS (2) 2004: 445-448 - [c26]Tao Wan, Malgorzata Chrzanowska-Jeske:
Prediction of interconnect net-degree distribution based on Rent's rule. SLIP 2004: 107-114 - [c25]Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske:
Substrate noise optimization in early floorplanning for mixed signal SOCs. SoCC 2004: 301-304 - 2003
- [j8]Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 730-741 (2003) - [j7]Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola:
Board-level multiterminal net assignment for the partial cross-bar architecture. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 511-514 (2003) - [c24]Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang:
Core-based SoC test scheduling using evolutionary algorithm. IEEE Congress on Evolutionary Computation 2003: 1716-1723 - [c23]Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske:
Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. ICCAD 2003: 100-106 - [c22]Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske:
Graph-based approach to evaluate net routability of a floorplan. ISCAS (5) 2003: 465-468 - [c21]Malgorzata Chrzanowska-Jeske, Benyi Wang, Garrison W. Greenwood:
Floorplanning with performance-based clustering. ISCAS (4) 2003: 724-727 - 2002
- [j6]Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Marek A. Perkowski:
Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs. VLSI Design 14(1): 13-21 (2002) - [j5]Marek A. Perkowski, Bogdan J. Falkowski, Malgorzata Chrzanowska-Jeske, Rolf Drechsler:
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts. VLSI Design 14(1): 35-52 (2002) - [c20]Malgorzata Chrzanowska-Jeske, Garrison W. Greenwood, Benyi Wang:
Combining evolution strategies with Lagrangian relaxation for constructing nonslicing VLSI floorplans with soft modules. IEEE Congress on Evolutionary Computation 2002: 1261-1266 - [c19]Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings:
Board-level multiterminal net assignment. ACM Great Lakes Symposium on VLSI 2002: 130-135 - [c18]Benyi Wang, Malgorzata Chrzanowska-Jeske, Garrison W. Greenwood:
ELF-SP - evolutionary algorithm for non-slicing floorplans with soft modules. ICECS 2002: 681-684 - [c17]Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD 2002: 56-61 - 2001
- [c16]Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola:
Regular Realization of Symmetric Functions Using Reversible Logic. DSD 2001: 245-253 - [c15]Malgorzata Chrzanowska-Jeske:
Generalized symmetric variables. ICECS 2001: 1147-1150 - [c14]Wei Wang, Malgorzata Chrzanowska-Jeske:
A global approach to the variable ordering problem in PSBDDs. ISCAS (5) 2001: 117-120 - 2000
- [c13]Malgorzata Chrzanowska-Jeske, Wei Wang, Jing Xia, Marcin Jeske:
Disjunctive Decomposition of Switching Functions Using Symmetry Information. SBCCI 2000: 69-74
1990 – 1999
- 1999
- [j4]Malgorzata Chrzanowska-Jeske, Yang Xu, Marek A. Perkowski:
Logic Synthesis for a Regular Layout. VLSI Design 10(1): 35-55 (1999) - [c12]Malgorzata Chrzanowska-Jeske:
Generalized symmetric and generalized pseudo-symmetric functions. ICECS 1999: 343-346 - [c11]Malgorzata Chrzanowska-Jeske:
Regular symmetric arrays for non-symmetric functions. ISCAS (1) 1999: 391-394 - 1998
- [c10]Malgorzata Chrzanowska-Jeske, Yang Xu:
Variable ordering for regular layout representation. ICECS 1998: 93-96 - 1996
- [c9]Malgorzata Chrzanowska-Jeske, Chungping Guo:
Synthesis approach to multi-level regular representation for combinational circuits. ICECS 1996: 374-377 - 1995
- [j3]Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Andisheh Sarabi, Ingo Schäfer:
Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions. VLSI Design 3(3-4): 301-313 (1995) - [j2]Ning Song, Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Andisheh Sarabi:
A New Design Methodology for Two-Dimensional Logic Arrays. VLSI Design 3(3-4): 315-332 (1995) - [c8]Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Naveen Buddi:
Tree restructuring approach to mapping problem in cellular-architecture FPGAs. EURO-DAC 1995: 60-65 - [c7]Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe:
Layout synthesis for datapath designs. EURO-DAC 1995: 86-90 - 1994
- [j1]Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Edmund Pierzchala, Alan J. Coppola:
An Exact Solution to the Fitting Problem in the Application Specific State Machine Device. J. Circuits Syst. Comput. 4(2): 173-190 (1994) - [c6]Andisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski:
A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays. DAC 1994: 321-326 - [c5]Ning Song, Malgorzata Chrzanowska-Jeske:
Output Column Folding for Cellular-Architecture FPGAs. ISCAS 1994: 237-240 - [c4]Marek A. Perkowski, Malgorzata Chrzanowska-Jeske:
Multiple-Valued-Input TANT Networks. ISMVL 1994: 334-341 - 1993
- [c3]Malgorzata Chrzanowska-Jeske, Steffen Goller:
Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device. EURO-DAC 1993: 39-44 - [c2]Malgorzata Chrzanowska-Jeske, Steffen Goller, Ingo Schäfer:
An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD. ISCAS 1993: 1782-1785 - 1990
- [c1]Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Tuhar Shah:
Minimization of multioutput TANT networks for unlimited fan-in network model. ICCD 1990: 360-363
Coauthor Index
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