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Chin-Yu Lin
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Publications
- 2018
- [j7]Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee:
A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique. IEEE J. Solid State Circuits 53(5): 1508-1517 (2018) - 2016
- [j6]Chin-Yu Lin, Tai-Cheng Lee:
A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 929-938 (2016) - [j5]Chin-Yu Lin, Chien-Heng Wong, Chia-Hau Hsu, Yen-Hsin Wei, Tai-Cheng Lee:
A 200-MS/s Phase-Detector-Based Comparator With 400-μVrms Noise. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 813-817 (2016) - [c13]Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee:
27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration. ISSCC 2016: 468-469 - 2014
- [c11]Yu-Hsuan Kang, Chin-Yu Lin, Tai-Cheng Lee:
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator. ISCAS 2014: 1328-1331 - [c10]Chin-Yu Lin, Tai-Cheng Lee:
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique. VLSIC 2014: 1-2 - 2013
- [c7]Chin-Yu Lin, Yen-Chuan Huang, Tai-Cheng Lee:
Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies. VLSI-DAT 2013: 1-4 - [c6]Chin-Yu Lin, Tai-Cheng Lee:
Jitter error cancellation technique in digital domain for ADC. VLSI-DAT 2013: 1-4 - 2010
- [c4]Chin-Yu Lin, Chun-Yu Chiang, Tai-Cheng Lee:
An offset phase-locked loop spread spectrum clock generator for SATA III. CICC 2010: 1-4
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