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ORCIDValerio Vignoli
- > Home > Persons > Valerio Vignoli
Publications
- 2019
[j37]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019)- 2010
- [j19]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy. J. Circuits Syst. Comput. 19(4): 879-895 (2010) - 2007
- [j14]Tommaso Addabbo, Massimo Alioto, Ada Fort, Antonio Pasini, Santina Rocchi, Valerio Vignoli:
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(4): 816-828 (2007) - [j13]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(9): 1916-1928 (2007) - [c18]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms. ECCTD 2007: 368-371 - [c16]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. ISCAS 2007: 693-696 - [c15]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. ISCAS 2007: 861-864 - 2006
- [j12]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
A feedback strategy to improve the entropy of a chaos-based random bit generator. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 326-337 (2006) - [j11]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Low-hardware complexity PRBGs based on a piecewise-linear chaotic map. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 329-333 (2006) - [j10]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Exploiting Hysteresys in MCML Circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1170-1174 (2006) - [j9]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits. IEEE Trans. Instrum. Meas. 55(5): 1451-1458 (2006) - [c14]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Efficient Post-Processing Module for a Chaos-based Random Bit Generator. ICECS 2006: 1224-1227 - [c13]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
A technique to design high entropy chaos-based true random bit generators. ISCAS 2006 - [c12]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Analysis and design of MCML gates with hysteresis. ISCAS 2006 - [c11]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. PATMOS 2006: 593-602 - [c10]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. PATMOS 2006: 624-633 - 2005
- [c9]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Long period pseudo random bit generators derived from a discretized chaotic map. ISCAS (2) 2005: 892-895 - [c8]Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
An approach to the design of PFSCL gates. ISCAS (3) 2005: 2437-2440 - 2004
- [j5]Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli:
An efficient implementation of PRNGs based on the digital sawtooth map. Int. J. Circuit Theory Appl. 32(6): 615-627 (2004) - [j4]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Modeling and evaluation of positive-feedback source-coupled logic. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(12): 2345-2355 (2004) - [c7]Tommaso Addabbo, Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli:
Hardware-efficient PRBGs based on 1-D piecewise linear chaotic maps. ICECS 2004: 242-245 - [c6]Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Positive-Feedback Source-Coupled Logic: a delay model. ISCAS (2) 2004: 641-644 - 2003
- [c5]Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli:
Analysis and design of digital PRNGS based on the discretized sawtooth map. ICECS 2003: 427-430
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