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ORCIDShahrzad Mirkhani
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2010 – 2019
- 2019
[c17]Balavinayagam Samynathan, Keith Chapman, Mehdi Nik, Behnam Robatmili, Shahrzad Mirkhani, Maysam Lavasani:
Computational Storage For Big Data Analytics. ADMS@VLDB 2019: 55-63- 2018
- [j2]Eric Cheng
, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1839-1852 (2018) - 2017
- [c16]Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra:
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD 2017: 593-596 - [i2]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). CoRR abs/1709.09921 (2017) - 2016
- [c15]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. DAC 2016: 68:1-68:6 - [i1]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores. CoRR abs/1604.03062 (2016) - 2015
- [c14]Shahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher, Jacob A. Abraham:
Efficient soft error vulnerability estimation of complex designs. DATE 2015: 103-108 - [c13]Shahrzad Mirkhani, Balavinayagam Samynathan, Jacob A. Abraham:
In-depth soft error vulnerability analysis using synthetic benchmarks. VTS 2015: 1-6 - 2014
- [c12]Shahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham:
Rethinking error injection for effective resilience. ASP-DAC 2014: 390-393 - [c11]Shahrzad Mirkhani, Jacob A. Abraham:
EAGLE: A regression model for fault coverage estimation using a simulation based metric. ITC 2014: 1-10 - [c10]Shahrzad Mirkhani, Jacob A. Abraham:
Fast evaluation of test vector sets using a simulation-based statistical metric. VTS 2014: 1-6 - 2013
- [c9]Hyungmin Cho, Shahrzad Mirkhani, Chen-Yong Cher, Jacob A. Abraham, Subhasish Mitra:
Quantitative evaluation of soft error injection techniques for robust system design. DAC 2013: 101:1-101:10 - 2012
- [c8]Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow:
FALCON: Rapid statistical fault coverage estimation for complex designs. ITC 2012: 1-10
2000 – 2009
- 2007
- [c7]Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi:
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. FDL 2007: 171-176 - [c6]Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi:
RT level reliability enhancement by constructing dynamic TMRS. ACM Great Lakes Symposium on VLSI 2007: 172-175 - 2006
- [c5]Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi:
ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs. ATS 2006: 195-202 - 2005
- [c4]Shahrzad Mirkhani, Zainalabedin Navabi:
Enhancing Fault Simulation Performance by Dynamic Fault Clustering. Asian Test Symposium 2005: 278-283 - 2004
- [j1]Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi:
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. J. Electron. Test. 20(6): 575-589 (2004) - 2002
- [c3]Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi:
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. Asian Test Symposium 2002: 374- - 2001
- [c2]Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi:
Fault Simulation for VHDL Based Test Bench and BIST Evaluation. Asian Test Symposium 2001: 396- - [c1]Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi:
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. DATE 2001: 823
Coauthor Index
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