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2020 – today
- 2024
[c6]Juzheng Liu, Ayman Shabra, Stacy Ho, Gabriele Manganaro, Mike Shuo-Wei Chen:
A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. VLSI Technology and Circuits 2024: 1-2
2010 – 2019
- 2019
- [c5]Ayman Shabra, Padraig Cooney, Adalberto Cantoni, Joshua Bamford, Stacy Ho, Michael Ashburn:
A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD. CICC 2019: 1-4 - 2018
- [c4]Tao He, Michael Ashburn, Stacy Ho, Yi Zhang, Gabor C. Temes:
A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. ISSCC 2018: 230-232 - 2016
- [c3]Gilad Yahalom, Stacy Ho, Alice Wang, Uming Ko, Anantha P. Chandrakasan:
Analog-digital partitioning and coupling in 3D-IC for RF applications. 3DIC 2016: 1-4 - 2015
- [j2]Stacy Ho, Chi-Lun Lo, Jiayun Ru, Jialin Zhao:
A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS. IEEE J. Solid State Circuits 50(4): 908-919 (2015) - [j1]Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee:
A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS. IEEE J. Solid State Circuits 50(12): 2880-2890 (2015) - [c2]Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee:
15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS. ISSCC 2015: 1-3 - 2014
- [c1]Stacy Ho, Chi-Lun Lo, Zhiyu Ru, Jialin Zhao:
A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS. VLSIC 2014: 1-2
Coauthor Index
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