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2010 – 2019
- 2016
[c5]Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii:
A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. A-SSCC 2016: 17-20- [c4]Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii:
A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. VLSI Circuits 2016: 1-2 - 2014
- [c3]Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato:
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. VLSIC 2014: 1-2
2000 – 2009
- 2004
- [c2]Tomoyuki Ishii, Taro Osabe, Toshiyuki Mine, Toshiaki Sano, Bryan Atwood, Norifumi Kameshiro, Takao Watanabe, Kazuo Yano:
SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories. CICC 2004: 457-463 - [c1]Bryan Atwood, Tomoyuki Ishii, Takao Watanabe, Toshiyuki Mine, Norifumi Kameshiro, Toshiaki Sano, Kazuo Yano:
A cavity channel SESO embedded memory with low standby-power techniques. ESSCIRC 2004: 351-354
1990 – 1999
- 1999
- [j1]Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi, Tokuo Kure, Koichi Seki:
Single-electron memory for giga-to-tera bit storage. Proc. IEEE 87(4): 633-651 (1999)
Coauthor Index
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