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ORCIDDerong Liu 0002
Person information
- affiliation: Cadence Design Systems, Inc., Austin, TX, USA
- affiliation: University of Texas at Austin, Department of Electrical and Computer Engineering, TX, USA
Other persons with the same name
- Derong Liu — disambiguation page
- Derong Liu 0001
![[0000-0003-3715-4778]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0003-3715-4778")
— University of Science and Technology Beijing, School of Automation and Electrical Engineering, China (and 5 more)
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Journal Articles
- 2019
[j5]Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1147-1160 (2019)- 2018
- [j4]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 231-244 (2018) - 2017
- [j3]Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Incremental Layer Assignment Driven by an External Signoff Timing Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1126-1139 (2017) - [j2]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental Layer Assignment for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 22(4): 75:1-75:25 (2017) - 2016
- [j1]Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan:
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1618-1629 (2016)
Conference and Workshop Papers
- 2019
- [c9]Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan:
Hardware-software co-design of slimmed optical neural networks. ASP-DAC 2019: 705-710 - [c8]Zheng Zhao, Derong Liu, Zhoufeng Ying, Biying Xu, Chenghao Feng, Ray T. Chen, David Z. Pan:
Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis. DATE 2019: 1567-1570 - [c7]Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan:
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD 2019: 19-26 - 2018
- [c6]Derong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
OPERON: optical-electrical power-efficient route synthesis for on-chip signals. DAC 2018: 75:1-75:6 - [c5]Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh:
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD 2018: 10-17 - 2017
- [c4]Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. DAC 2017: 18:1-18:6 - 2016
- [c3]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental layer assignment for critical path timing. DAC 2016: 85:1-85:6 - 2015
- [c2]Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan:
OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. DAC 2015: 129:1-129:6 - [c1]Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan:
TILA: Timing-Driven Incremental Layer Assignment. ICCAD 2015: 110-117
Coauthor Index
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